PEB3081FV14XP Lantiq, PEB3081FV14XP Datasheet - Page 60

• Manufacturer Part Number: PEB3081FV14XP
• Manufacturer: Lantiq

Specifications of PEB3081FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

PEB 3081
PEF 3081
Description of Functional Blocks
Preliminary
3.5
Control of Layer-1
The layer-1 activation / deactivation can be controlled by an internal state machine via
the IOM-2 C/I0 channel or by software via the microcontroller interface directly. In the
default state the internal layer-1 state machine of the SBCX-X is used.
By setting the L1SW bit in the TR_CONF0 register the internal state machine can be
disabled and the layer-1 commands, which are normally generated by the internal state
machine are written directly in the TR_CMD register or indications read from the
TR_STA register respectively.The SBCX-X layer-1 control flow is shown in
Figure
31.
Figure 31
Layer-1 Control
In the following sections the layer-1 control by the SBCX-X state machine will be
described. For the description of the IOM-2 C/I0 channel see also
Chapter
3.7.4.
The layer-1 functions are controlled by commands issued via the CIX0 register. These
commands, sent over the IOM-2 C/I channel 0 to layer-1, trigger certain procedures,
such as activation/deactivation, switching of test loops and transmission of special pulse
patterns. These procedures are governed by layer-1 state diagrams. Responses from
layer 1 are obtained by reading the CIR0 register after a CIC interrupt (ISTA).
The state diagrams of the SBCX-X are shown in
Figure 33
and
Figure
34. The
activation/deactivation implemented by the SBCX-X agrees with the requirements set
forth in ITU recommendations. State identifiers F1-F8 are in accordance with ITU I.430.
Data Sheet
60
2000-09-27