PEB3081FV14XP Lantiq, PEB3081FV14XP Datasheet - Page 170

• Manufacturer Part Number: PEB3081FV14XP
• Manufacturer: Lantiq

Specifications of PEB3081FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Preliminary
• If RSS = ’00’ no above listed reset source is selected and therefore no reset is
• Watchdog Timer
• If RSS = ’10’ is selected the following two reset sources generate a reset pulse of
After a reset pulse generated by the SBCX-X and the corresponding interrupt (WOV or
CIC) the actual reset source can be read from the ISTA.
4.4.6
Value after reset: 00
MODE2
INT_POL ... Interrupt Polarity
Selects the polarity of the interrupt pin INT.
0: low active with open drain characteristic (default)
1: high active with push pull characteristic
PPSDX ... Push/Pull Output for SDX (SCI Interface)
0: The SDX pin has open drain characteristic
1: The SDX pin has push/pull characteristic
Data Sheet
generated at RSTO.
After the selection of the watchdog timer (RSS = ’11’) the timer is reset and started.
During every time period of 128 ms the microcontroller has to program the WTC1 and
WTC2 bits in two consecutive bit pattern (see description of the WTC1, 2 bits)
otherwise the watchdog timer expires and a reset pulse of 125 µs
generated. Deactivation of the watchdog timer is only possible with a hardware reset.
125 µs
- External (Subscriber) Awake (EAW)
The EAW input pin serves as a request signal from the subscriber to initiate the awake
function in a terminal and generates a reset pulse (in TE mode only).
- Exchange Awake (C/I Code)
A C/I Code change generates a reset pulse.
7
MODE2 - Mode2 Register
t  250µs at the RSTO pin:
0
H
0
0
0
170
INT_
POL
0
Detailed Register Description
0
0
PPSDX RD/WR (63)
t 250 µs is
PEB 3081
PEF 3081
2000-09-27