PEB3081FV14XP Lantiq, PEB3081FV14XP Datasheet - Page 52

• Manufacturer Part Number: PEB3081FV14XP
• Manufacturer: Lantiq

Specifications of PEB3081FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Preliminary
3.3.8
If MODE1.CFS is set to ’0’, the clocks are also provided in power down state, whereas
if CFS is set to ’1’ only the analog level detector is active in power down state. All clocks,
including the IOM-2 interface, are stopped (DD, DU are ’high’, DCL and BCL are ’low’).
An activation initiated from the exchange side will have the consequence that a clock
signal is provided automatically if TR_CONF0.LDD is set to ’0’. If TR_CONF0.LDD is set
to ’1’ the microcontroller has to take care of an interrupt caused by the level detect circuit
(ISTATR.LD)
From the terminal side an activation must be started by setting and resetting the SPU-
bit in the IOM_CR register and writing TIM to the CIX0 register or by resetting
MODE1.CFS=0.
3.3.9
The layer-1 part of the SBCX-X can be enabled/disabled by configuration (see
Figure
By default all layer-1 functions with the exception of the transmitter buffer is enabled
(DIS_TR = ’0’, DIS_TX = ’1’). With several terminals connected to the S/T interface,
another terminal may keep the interface activated although the SBCX-X does not
establish a connection. The receiver will monitor for incoming calls in this configuration.
If the transceiver is disabled (DIS_TR = ’1’) all layer-1 functions are disabled including
the level detection circuit of the receiver. In this case the power consumption of the
Layer-1 is reduced to a minimum. The DCL and FSC pins become input.
Figure 26
Data Sheet
26) with the two bits TR_CONF0.DIS_TR and TR_CONF2.DIS_TX .
Level Detection Power Down
Transceiver Enable/Disable
Disabling of S/T Transmitter
TR_CONF0.DIS_TR
52
TR_CONF2.DIS_TX
Description of Functional Blocks
’1’
’0’
PEB 3081
PEF 3081
2000-09-27