PEB3081FV14XP Lantiq, PEB3081FV14XP Datasheet - Page 32

• Manufacturer Part Number: PEB3081FV14XP
• Manufacturer: Lantiq

Specifications of PEB3081FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Preliminary
3.2.3
Special events in the device are indicated by means of a single interrupt output, which
requests the host to read status information from the device or transfer data from/to the
device.
Since only one interrupt request pin (INT) is provided, the cause of an interrupt must be
determined by the host reading the interrupt status registers of the device.
The structure of the interrupt status registers is shown in
Figure 8
All five interrupt bits in the ISTA register point at interrupt sources in the Monitor handler
(MOS), C/I handler (CIC), the transceiver (TRAN), the synchronous transfer (ST) and the
auxiliary interrupts (AUXI).
All these interrupt sources are described in the corresponding chapters. After the device
has requested an interrupt activating the interrupt pin (INT), the host must read first the
device interrupt status register (ISTA) in the associated interrupt service routine. The
interrupt pin of the device remains active until all interrupt sources are cleared by reading
the corresponding interrupt register. Therefore it is possible that the interrupt pin is still
active when the interrupt service routine is finished.
Each interrupt indication of the interrupt status registers can selectively be masked by
setting the respective bit in the MASK register.
For some interrupt controllers or hosts it might be necessary to generate a new edge on
the interrupt line to recognize pending interrupts. This can be done by masking all
interrupts at the end of the interrupt service routine (writing FF
and write back the old mask to the MASK register.
Data Sheet
MASK
TRAN
MOS
Interrupt
AUX
CIC
Interrupt Structure
ST
Interrupt Status and Mask Registers
TRAN
MOS
ISTA
AUX
CIC
ST
STOV21
STOV20
STOV11
STOV10
STI21
STI20
STI11
STI10
MSTI
32
STOV21
STOV20
STOV11
STOV10
MOCR
STI21
STI20
STI11
STI10
MRE
MIE
STI
MASKTR
SQW
SQC
RIC
LD
Description of Functional Blocks
ACK21
ACK20
ACK11
ACK10
ASTI
ISTATR
MOSR
SQW
MDR
SQC
MER
MDA
MAB
RIC
LD
Figure
H
AUXM
WOV
CIX1
EAW
CI1E
into the MASK register)
TIN
8.
3081_16.vsd
WOV
CIR0
EAW
AUXI
CIC0
CIC1
TIN
PEB 3081
PEF 3081
2000-09-27