PEB3081FV14XP Lantiq, PEB3081FV14XP Datasheet - Page 110

• Manufacturer Part Number: PEB3081FV14XP
• Manufacturer: Lantiq

Specifications of PEB3081FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Preliminary
The two corresponding status bits CIC0 and CIC1 are read in CIR0 register. CIC1 can
be individually disabled by clearing the enable bit CI1E in the CIX1 register. In this case
the occurrence of a code change in CIR1 will not be displayed by CIC1 until the
corresponding enable bit has been set to one.
Bits CIC0 and CIC1 are cleared by a read of CIR0.
An interrupt status is indicated every time a valid new code is loaded in CIR0 or CIR1.
The CIR0 is buffered with a FIFO size of two. If a second code change occurs in the
received C/I channel 0 before the first one has been read, immediately after reading of
CIR0 a new interrupt will be generated and the new code will be stored in CIR0. If several
consecutive codes are detected, only the first and the last code is obtained at the first
and second register read, respectively.
For CIR1 no FIFO is available. The actual code of the received C/I channel 1 is always
stored in CIR1.
Figure 58
3.7.5
D-channel access control is defined to guarantee all connected TEs and HDLC
controllers a fair chance to transmit data in the D-channel. Collisions are possible
• on the IOM-2 interface if there is more than one HDLC controller connected or
• on the S-interface when there is more than one terminal connected in a point to
Both arbitration mechanisms are implemented in the SBCX-X and will be described in
the following two chapters.
Data Sheet
multipoint configuration (NT
D-Channel Access Control
CIC Interrupt Structure
TRAN
MASK
WOV
MOS
CIC
ST
Interrupt
TRAN
ISTA
WOV
MOS
CIC
ST
TE1 … TE8).
110
CI1E
CIX1
Description of Functional Blocks
CIC0
CIC1
CIR0
PEB 3081
PEF 3081
2000-09-27