PEB3081FV14XP Lantiq, PEB3081FV14XP Datasheet - Page 112

• Manufacturer Part Number: PEB3081FV14XP
• Manufacturer: Lantiq

Specifications of PEB3081FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

PEB 3081
PEF 3081
Description of Functional Blocks
Preliminary
In the case of an access request to the C/I channel, the SBCX-X checks the Bus
Accessed-bit BAC (bit 5 of last octet of CH2 on DU, see
Figure
60) for the status "bus
free“, which is indicated by a logical ’1’. If the bus is free, the SBCX-X transmits its
individual TIC bus address TAD. The SBCX-X sends its TIC bus address TAD and
compares it bit by bit with the value on DU. If a sent bit set to ’1’ is read back as ’0’
because of the access of another source with a lower TAD wishing access to D- or C/I-
channel, the SBCX-X withdraws immediately from the TIC bus, i.e. the remaining TAD
bits are not transmitted. The TIC bus is occupied by the device which sends its address
error-free. If more than one device attempt to seize the bus simultaneously, the one with
the lowest address values wins. This one will set BAC=0 on TIC bus and starts D-
channel transmission in the same frame.
DU
Figure 60
Structure of Last Octet of Ch2 on DU
When the TIC bus is seized by the ICC, the bus is identified to other devices as occupied
via the DU Ch2 Bus Accessed-bit state ’0’ until the access request is withdrawn. After a
successful bus access, the ICC is automatically set into a lower priority class, that is, a
new bus access cannot be performed until the status "bus free" is indicated in two
successive frames.
If none of the devices connected to the IOM-2 interface request access to the D and C/
I channels, the TIC bus address 7 will be present. The device with this address will
therefore have access, by default, to the D and C/I channels.
Data Sheet
112
2000-09-27