PEB3081FV14XP Lantiq, PEB3081FV14XP Datasheet - Page 157

• Manufacturer Part Number: PEB3081FV14XP
• Manufacturer: Lantiq

Specifications of PEB3081FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Preliminary
4.3.9
Value after reset: 00
SDSx_CR ENS_
Register
SDS1_CR
SDS2_CR
This register is used to select position and length of the strobe signals. The length can
be any combination of two 8-bit timeslot (ENS_TSS, ENS_TSS+1) and one 2-bit timeslot
(ENS_TSS+3).
For general information please refer to
ENS_TSS ... Enable Serial Data Strobe of timeslot TSS
ENS_TSS+1 ... Enable Serial Data Strobe of timeslot TSS+1
0: The serial data strobe signal SDSx is inactive during TSS, TSS+1
1: The serial data strobe signal SDSx is active during TSS, TSS+1
ENS_TSS+3 ... Enable Serial Data Strobe of timeslot TSS+3 (D-Channel)
0: The serial data strobe signal SDSx is inactive during the D-channel (bit7, 6) of TSS+3
1: The serial data strobe signal SDSx is active during the D-channel (bit7, 6) of TSS+3
TSS ... Timeslot Selection
Selects one of 32 timeslots on the IOM-2 interface (with respect to FSC) during which
SDSx is active high or provides a strobed BCL clock output (see SDS_CONF.SDS1/
2_BCL). The data strobe signal allows standard data devices to access a programmable
channel.
Data Sheet
7
SDSx_CR - Control Register Serial Data Strobe x
TSS
Register Address
55
56
TSS+1
ENS_
H
H
H
TSS+3
ENS_
Chapter 3.7.2
157
Value after Reset
00
00
H
H
TSS
and
Detailed Register Description
Chapter
0
3.7.2.2.
PEB 3081
PEF 3081
2000-09-27
RD/WR
(55-56)