CY7C68001-56LTXC Cypress Semiconductor Corp, CY7C68001-56LTXC Datasheet - Page 9

• Manufacturer Part Number: CY7C68001-56LTXC
• Description: IC USB EZ-USB SX2 HS 56VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr
• Type: USBr

Specifications of CY7C68001-56LTXC

• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2932

3.0
3.1
SX2 operates at two of the three rates defined in the Universal Serial Bus Specification Revision 2.0, dated April 27, 2000:
SX2 does not support the low-speed signaling rate of 1.5 Mbits/s.
3.2
SX2 features:
3.3
During the power-up sequence, internal logic of the SX2 checks for the presence of an I
an EEPROM, it will boot off the EEPROM. When the presence of an EEPROM is detected, the SX2 checks the value of first byte.
If the first byte is found to be a 0xC4, the SX2 loads the next two bytes into the IFCONFIG and POLAR registers, respectively. If
the fourth byte is also 0xC4, the SX2 enumerates using the descriptor in the EEPROM, then signals to the external master when
enumeration is complete via an ENUMOK interrupt (Section 3.4). If no EEPROM is detected, the SX2 relies on the external master
for the descriptors. Once this descriptor information is receive from the external master, the SX2 will connect to the USB bus and
enumerate.
3.3.1
The valid sequence of bytes in the EEPROM are displayed below.
Notes:
Document #: 38-08013 Rev. *B
Table 3-1. Descriptor Length Set to 0x06: Default Enumeration
Byte Index
1.
2.
• Full-speed, with a signaling bit rate of 12 Mbits/s
• High-speed, with a signaling bit rate of 480 Mbits/s.
• A selectable 8- or 16-bit bidirectional data bus
• An address bus for selecting the FIFO or Command Interface.
• 0xC4: This initial byte tells the SX2 that this is a valid EEPROM with configuration information.
• IFCONFIG: This byte contains the settings for the IFCONFIG register. The IFCONFIG register bits are defined in Section 7.1.
• POLAR: This byte contains the polarities of the interface signals. The POLAR register bits are defined in Section 7.3. If the
• Descriptor: This next byte determines whether or not the SX2 loads the descriptor from the EEPROM. If this byte = 0xC4,
If the external master requires an interface configuration different from the default, that interface can be specified in this byte.
external master requires signal polarities different from the default, those polarities can be specified in this byte.
the SX2 will load the descriptor starting with the next byte. If this byte does not equal 0xC4, the SX2 will wait for descriptor
information from the external master.
Because there is no direct way to detect which EEPROM type (single or double address) is connected, SX2 uses the EEPROM address pins A2, A1, and A0
to determine whether to send out one or two bytes of address. Single-byte address EEPROMs (24LC01, etc.) should be strapped to address 000 and double-
byte EEPROMs (24LC64, etc.) should be strapped to address 001.
The SCL and SDA pins must be pulled up for this detection method to work properly, even if an EEPROM is not connected. Typical pull-up values are 2.2K – 10K
Ohms.
10
11
0
1
2
3
4
5
6
7
8
9
USB Signaling Speed
Buses
Boot Methods
EEPROM Organization
Functional Overview
0xC4
IFCONFIG
POLAR
0xC4
Descriptor Length (LSB):0x06
Descriptor Length (MSB): 0x00
VID (LSB)
VID (MSB)
PID (LSB)
PID (MSB)
DID (LSB)
DID (MSB)
Description
Table 3-2. Descriptor Length Not Set to 0x06
Byte Index
0
1
2
3
4
5
6
7
8
..
..
..
0xC4
IFCONFIG
POLAR
0xC4
Descriptor Length (LSB)
Descriptor Length (MSB
Descriptor[0]
Descriptor[1]
Descriptor[2]
....
....
....
2
C-compatible EEPROM.
Description
CY7C68001
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