CY7C68001-56LTXC Cypress Semiconductor Corp, CY7C68001-56LTXC Datasheet - Page 23

• Manufacturer Part Number: CY7C68001-56LTXC
• Description: IC USB EZ-USB SX2 HS 56VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr
• Type: USBr

Specifications of CY7C68001-56LTXC

• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2932

These flags can be programmed to represent various FIFO flags using four select bits for each FIFO. The 4-bit coding for all four
flags is the same, as shown in the following table.
Table 7-2. FIFO Flag 4-bit Coding
For the default (0000) selection, the four FIFO flags are fixed-function as shown in the first table entry; the input pins FIFOADR[2:0]
select to which of the four FIFOs the flags correspond. These pins are decoded as shown in Table 3-3.
The other (non-zero) values of FLAGx[3:0] allow the designer to independently configure the four flag outputs FLAGA-FLAGD to
correspond to any flag-Programmable, Full, or Empty-from any of the four endpoint FIFOs. This allows each flag to be assigned
to any of the four FIFOs, including those not currently selected by the FIFOADR [2:0] pins. For example, the external master
could be filling the EP2IN FIFO with data while also checking the empty flag for the EP4OUT FIFO.
7.3
This register controls the polarities of FIFO pin signals and the WAKEUP pin.
7.3.1
This flag sets the polarity of the WAKEUP pin. If WUPOL = 0 (default), the polarity is active LOW. If WUPOL=1, the polarity is
active HIGH.
7.3.2
This flag selects the polarity of the PKTEND pin. If PKTEND = 0 (default), the polarity is active LOW. If PKTEND = 1, the polarity
is active HIGH.
Document #: 38-08013 Rev. *B
FLAGSCD
Bit #
Bit Name
Read/Write
Reset
POLAR
Bit #
Bit Name
Read/Write
Reset
FLAGx3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
POLAR Register 0x04
Bit 7: WUPOL
Bit 5: PKTEND
FLAGD3
WUPOL
R/W
R/W
FLAGx2
7
0
7
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FLAGD2
R/W
R/W
6
0
6
0
0
FLAGx1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
PKTEND
FLAGD1
R/W
R/W
5
0
5
0
FLAGx0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
FLAGD0
SLOE
R/W
R/W
4
0
4
0
FLAGA = PF, FLAGB = FF, FLAGC = EF, FLAGD = CS# (actual
FIFO is selected by FIFOADR[2:0] pins)
Reserved
Reserved
Reserved
EP2 PF
EP4 PF
EP6 PF
EP8 PF
EP2 EF
EP4 EF
EP6 EF
EP8 EF
EP2 FF
EP4 FF
EP6 FF
EP8 FF
FLAGC3
SLRD
R/W
R/W
3
0
3
0
FLAGC2
Pin Function
SLWR
R/W
R/W
2
0
2
0
FLAGC1
R/W
R/W
EF
1
0
1
0
CY7C68001
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FLAGC0
R/W
R/W
FF
0
0
0
0
0x03
0x04