CY7C68001-56LTXC Cypress Semiconductor Corp, CY7C68001-56LTXC Datasheet - Page 5

• Manufacturer Part Number: CY7C68001-56LTXC
• Description: IC USB EZ-USB SX2 HS 56VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr
• Type: USBr

Specifications of CY7C68001-56LTXC

• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2932

CY7C68001
LIST OF FIGURES
FIGURE 1-1. BLOCK DIAGRAM ............................................................................................................ 7
FIGURE 2-1. EXAMPLE USB SYSTEM DIAGRAM ............................................................................... 8
FIGURE 3-1. ENDPOINT CONFIGURATION ....................................................................................... 12
FIGURE 6-1. CY7C68001 56-PIN SSOP PIN ASSIGNMENT .............................................................. 17
FIGURE 6-2. CY7C68001 56-PIN QFN ASSIGNMENT........................................................................ 18
FIGURE 11-1. COMMAND SYNCHRONOUS READ TIMING DIAGRAM............................................ 32
FIGURE 11-2. COMMAND SYNCHRONOUS WRITE TIMING DIAGRAM .......................................... 33
FIGURE 11-3. COMMAND ASYNCHRONOUS READ TIMING DIAGRAM ......................................... 34
FIGURE 11-4. COMMAND ASYNCHRONOUS WRITE TIMING DIAGRAM........................................ 34
FIGURE 11-5. SLAVE FIFO SYNCHRONOUS READ TIMING DIAGRAM.......................................... 35
FIGURE 11-6. SLAVE FIFO SYNCHRONOUS WRITE TIMING DIAGRAM ........................................ 36
FIGURE 11-7. SLAVE FIFO SYNCHRONOUS PACKET END STROBE TIMING DIAGRAM ............ 37
FIGURE 11-8. SLAVE FIFO SYNCHRONOUS ADDRESS TIMING DIAGRAM .................................. 37
FIGURE 11-9. SLAVE FIFO ASYNCHRONOUS READ TIMING DIAGRAM ....................................... 38
FIGURE 11-10. SLAVE FIFO ASYNCHRONOUS WRITE TIMING DIAGRAM.................................... 38
FIGURE 11-11. SLAVE FIFO ASYNCHRONOUS PACKET END STROBE TIMING DIAGRAM........ 39
FIGURE 11-12. SLAVE FIFO ASYNCHRONOUS ADDRESS TIMING DIAGRAM.............................. 39
FIGURE 11-13. SLAVE FIFO ADDRESS TO FLAGS/DATA TIMING DIAGRAM ............................... 39
FIGURE 11-14. SLAVE FIFO OUTPUT ENABLE TIMING DIAGRAM ................................................ 40
FIGURE 11-15. SLAVE FIFO SYNCHRONOUS READ SEQUENCE AND TIMING DIAGRAM.......... 40
FIGURE 11-16. SLAVE FIFO SYNCHRONOUS SEQUENCE OF EVENTS DIAGRAM...................... 40
FIGURE 11-17. SLAVE FIFO SYNCHRONOUS WRITE SEQUENCE AND TIMING DIAGRAM ........ 41
FIGURE 11-18. SLAVE FIFO ASYNCHRONOUS READ SEQUENCE AND TIMING DIAGRAM ....... 42
FIGURE 11-19. SLAVE FIFO ASYNCHRONOUS READ SEQUENCE OF EVENTS DIAGRAM ........ 42
FIGURE 11-20. SLAVE FIFO ASYNCHRONOUS WRITE SEQUENCE AND TIMING DIAGRAM...... 43
FIGURE 14-1. CROSSSECTION OF THE AREA UNDERNEATH THE QFN PACKAGE ................... 47
FIGURE 14-2. (A) PLOT OF THE SOLDER MASK (WHITE AREA) ................................................... 47
FIGURE 14-2. (B) X-RAY IMAGE OF THE ASSEMBLY ...................................................................... 47
FIGURE 16-1. 56-LEAD SHRUNK SMALL OUTLINE PACKAGE ...................................................... 48
FIGURE 16-2. LF56A 56-PIN QFN PACKAGE .................................................................................... 49
Document #: 38-08013 Rev. *B
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