CY7C68001-56LTXC Cypress Semiconductor Corp, CY7C68001-56LTXC Datasheet - Page 39

• Manufacturer Part Number: CY7C68001-56LTXC
• Description: IC USB EZ-USB SX2 HS 56VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr
• Type: USBr

Specifications of CY7C68001-56LTXC

• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2932

11.3.7
Table 11-16. Slave FIFO Asynchronous Packet End Strobe Parameters
11.3.8
Table 11-17. Slave FIFO Asynchronous Address Parameters
11.4
Following timings is applicable to synchronous and asynchronous interface.
Table 11-18. Slave FIFO Address to Flags/Data Parameters
Document #: 38-08013 Rev. *B
t
t
t
t
t
t
t
t
Note:
11. tFAH for a write function has been experimentally found to be 70 ns. This is yet to be characterized. We recommend that you use a 70 ns.
PEpwl
PWpwh
XFLG
SFA
FAH
FAH
XFLG
XFD
Parameter
Parameter
Parameter
Slave FIFO Asynchronous Packet End Strobe
Slave FIFO Asynchronous Address
Slave FIFO Address to Flags/Data
PKTEND Pulse Width LOW
PKTEND Pulse Width HIGH
PKTEND to FLAGS Output Propagation Delay
FIFOADR[2:0] to RD/WR/PKTEND Set-up Time
SLRD/PKTEND to FIFOADR[2:0] Hold Time
SLWR to FIFOADR[2:0] Hold Time
FIFOADR[2:0] to FLAGS Output Propagation Delay
FIFOADR[2:0] to FIFODATA Output Propagation Delay
Figure 11-11. Slave FIFO Asynchronous Packet End Strobe Timing Diagram
FIFOADR[2:0]
SLRD/SLWR/PKTEND
Figure 11-12. Slave FIFO Asynchronous Address Timing Diagram
FIFOADR [2.0]
Figure 11-13. Slave FIFO Address to Flags/Data Timing Diagram
PKTEND
FLAGS
FLAGS
DATA
Description
Description
Description
t
SFA
t
PEpwl
t
XFLG
t
XFLG
[10]
t
XFD
N
t
PEpwh
N+1
[10]
t
FAH
TBD
Min.
Min.
Min.
50
50
10
20
[11]
[8]
[8]
Max.
Max.
Max.
10.7
14.3
70
CY7C68001
Page 39 of 50
Unit
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns