CY7C68001-56LTXC Cypress Semiconductor Corp, CY7C68001-56LTXC Datasheet - Page 4
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CY7C68001-56LTXC
Manufacturer Part Number
CY7C68001-56LTXC
Description
IC USB EZ-USB SX2 HS 56VQFN
Manufacturer
Cypress Semiconductor Corp
Series
CY7Cr
Type
USBr
Specifications of CY7C68001-56LTXC
Protocol
USB 2.0
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Package / Case
56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Drivers/receivers
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
428-2932
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C68001-56LTXC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
8.0 ABSOLUTE MAXIMUM RATINGS ................................................................................................ 31
9.0 OPERATING CONDITIONS ........................................................................................................... 31
10.0 DC ELECTRICAL CHARACTERISTICS ..................................................................................... 31
11.0 AC ELECTRICAL CHARACTERISTICS ..................................................................................... 32
12.0 DEFAULT DESCRIPTOR ............................................................................................................ 44
13.0 GENERAL PCB LAYOUT GUIDELINES ..................................................................................... 47
14.0 QUAD FLAT PACKAGE NO LEADS (QFN) PACKAGE DESIGN NOTES ................................ 47
15.0 ORDERING INFORMATION ........................................................................................................ 48
16.0 PACKAGE DIAGRAMS ............................................................................................................... 48
17.0 DOCUMENT REVISION HISTORY .............................................................................................. 50
Document #: 38-08013 Rev. *B
7.15 DESC Register 0x30 .............................................................................................................. 30
7.16 EP0BUF Register 0x31 ......................................................................................................... 30
7.17 SETUP Register 0x32 ............................................................................................................ 30
7.18 EP0BC Register 0x33 ............................................................................................................ 30
11.1 USB Transceiver ................................................................................................................... 32
11.2 Command Interface .............................................................................................................. 32
11.3 FIFO Interface ........................................................................................................................ 35
11.4 Slave FIFO Address to Flags/Data ...................................................................................... 39
11.5 Slave FIFO Output Enable .................................................................................................... 40
11.6 Sequence Diagram ................................................................................................................ 40
16.1 56-pin SSOP Package ........................................................................................................... 48
16.2 56-pin QFN Package ............................................................................................................. 49
11.2.1 Command Synchronous Read ................................................................................................. 32
11.2.2 Command Synchronous Write ................................................................................................. 33
11.2.3 Command Asynchronous Read ................................................................................................ 34
11.2.4 Command Asynchronous Write ............................................................................................... 34
11.3.1 Slave FIFO Synchronous Read .................................................................................................. 35
11.3.2 Slave FIFO Synchronous Write ................................................................................................ 36
11.3.3 Slave FIFO Synchronous Packet End Strobe ......................................................................... 37
11.3.4 Slave FIFO Synchronous Address ........................................................................................... 37
11.3.5 Slave FIFO Asynchronous Read ............................................................................................... 38
11.3.6 Slave FIFO Asynchronous Write ..............................................................................................38
11.3.7 Slave FIFO Asynchronous Packet End Strobe ........................................................................ 39
11.3.8 Slave FIFO Asynchronous Address ......................................................................................... 39
11.6.1 Single and Burst Synchronous Read Example ...................................................................... 40
11.6.2 Single and Burst Synchronous Write ........................................................................................ 41
11.6.3 Sequence Diagram of a Single and Burst Asynchronous Read ............................................ 42
11.6.4 Sequence Diagram of a Single and Burst Asynchronous Write ............................................. 43
TABLE OF CONTENTS
(continued)
CY7C68001
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