CY7C68001-56LTXC Cypress Semiconductor Corp, CY7C68001-56LTXC Datasheet - Page 22

• Manufacturer Part Number: CY7C68001-56LTXC
• Description: IC USB EZ-USB SX2 HS 56VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr
• Type: USBr

Specifications of CY7C68001-56LTXC

• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2932

7.1
7.1.1
This bit selects the clock source for the FIFOs. If IFCLKSRC = 0, the external clock on the IFCLK pin is selected. If IFCLKSRC
= 1 (default), an internal 30 or 48 MHz clock is used.
7.1.2
This bit selects the internal FIFO clock frequency. If 3048MHZ = 0, the internal clock frequency is 30 MHz. If 3048MHZ = 1
(default), the internal clock frequency is 48 MHz.
7.1.3
This bit selects if the IFCLK pin is driven. If IFCLKOE = 0 (default), the IFCLK pin is floated. If IFCLKOE = 1, the IFCLK pin is driven.
7.1.4
This bit controls the polarity of the IFCLK signal.
7.1.5
This bit controls whether the FIFO interface is synchronous or asynchronous. When ASYNC = 0, the FIFOs operate synchro-
nously. In synchronous mode, a clock is supplied either internally or externally on the IFCLK pin, and the FIFO control signals
function as read and write enable signals for the clock signal.
When ASYNC = 1 (default), the FIFOs operate asynchronously. No clock signal input to IFCLK is required, and the FIFO control
signals function directly as read and write strobes.
7.1.6
This bit instructs the SX2 to enter a low-power mode. When STANDBY=1, the SX2 will enter a low-power mode by turning off its
oscillator. The external master should write this bit after it receives a bus activity interrupt (indicating that the host has signaled
a USB suspend condition). If SX2 is disconnected from the USB bus, the external master can write this bit at any time to save
power. Once suspended, the SX2 is awakened either by resumption of USB bus activity or by assertion of its WAKEUP pin.
7.1.7
This bit controls the function of the FLAGD/CS# pin. When FLAGD/CS# = 0 (default), the pin operates as a slave chip select. If
FLAGD/CS# = 1, the pin operates as FLAGD.
7.1.8
This bit controls whether the internal pull-up resistor connected to D+ is pulled high or floating. When DISCON = 1 (default), the
pull-up resistor is floating simulating a USB unplug. When DISCON=0, the pull-up resistor is pulled high signaling a USB
connection.
7.2
The SX2 has four FIFO flags output pins: FLAGA, FLAGB, FLAGC, FLAGD.
Document #: 38-08013 Rev. *B
IFCONFIG
Bit #
Bit Name
Read/Write
Default
FLAGSAB
Bit #
Bit Name
Read/Write
Reset
• When IFCLKPOL=0, the clock has the polarity shown in all the timing diagrams in this data sheet (rising edge is the activating
• When IFCLKPOL=1, the clock is inverted (in some cases may help with satisfying data set-up times).
edge).
IFCONFIG Register 0x01
Bit 7: IFCLKSRC
Bit 6: 3048MHZ
Bit 5: IFCLKOE
Bit 4: IFCLKPOL
Bit 3: ASYNC
Bit 2: STANDBY
Bit 1: FLAGD/CS#
Bit 0: DISCON
FLAGSAB/FLAGSCD Registers 0x02/0x03
IFCLKSRC
FLAGB3
R/W
R/W
7
1
7
0
3048MHZ
FLAGB2
R/W
R/W
6
1
6
0
IFCLKOE
FLAGB1
R/W
R/W
5
0
5
0
IFCLKPOL
FLAGB0
R/W
R/W
4
0
4
0
FLAGA3
ASYNC
R/W
R/W
3
1
3
0
STANDBY
FLAGA2
R/W
R/W
2
0
2
0
FLAGD/CS#
FLAGA1
R/W
R/W
1
0
1
0
CY7C68001
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DISCON
FLAGA0
R/W
R/W
0
1
0
0
0x01
0x02