CY7C68001-56LTXC Cypress Semiconductor Corp, CY7C68001-56LTXC Datasheet - Page 27
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CY7C68001-56LTXC
Manufacturer Part Number
CY7C68001-56LTXC
Description
IC USB EZ-USB SX2 HS 56VQFN
Manufacturer
Cypress Semiconductor Corp
Series
CY7Cr
Type
USBr
Specifications of CY7C68001-56LTXC
Protocol
USB 2.0
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Package / Case
56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Drivers/receivers
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
428-2932
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C68001-56LTXC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
7.7.3
These three bits have a different meaning, depending on whether this is an IN or OUT endpoint, and if IN endpoint, the value of
the PKTSTAT bit.
7.7.3.1 IN Endpoints
When PKTSTAT = 0 (default), the PF considers when there are PKTS packets plus PFC bytes in the FIFO. PKTS(2:0) determines
how many packets are considered, according to the following table.
Table 7-5. PKTS Bits
When PKTSTAT = 1, the PF considers when there are PFC bytes in the FIFO, no matter how many packets are in the FIFO. The
PKTS(2:0) bits are ignored.
7.7.3.2 OUT Endpoints
The PF considers when there are PFC bytes in the FIFO.
7.8
For ISOCHRONOUS IN endpoints only, these registers determine the number of packets per frame (only one per frame for full-
speed mode) or microframe (up to three per microframe for high-speed mode), according to the following table.
Table 7-6. EPxISOINPKTS
7.9
The EPxxFLAGS provide an alternate way of checking the status of the endpoint FIFO flags. If enabled, the SX2 can interrupt
the external master when a flag is asserted, and the external master can read these two registers to determine the state of the
FIFO flags. If the INFM1 and/or OEP1 bits are set, then the EPxEF and EPxFF bits are actually empty +1 and full –1.
Document #: 38-08013 Rev. *B
EP2ISOINOKTS, EP4ISOINPKTS, EP6ISOINPKTS, EP8ISOINPKTS
Bit #
Bit Name
Read/Write
Reset
EP24FLAGS
Bit #
Bit Name
Read/Write
Reset
PKTSTAT
IN:PKTS(2:0)/OUT:PFC[12:10] EPxPFH[5:3]
EPxISOINPKTS Registers 0x1A–0x1D
EPxxFLAGS Registers 0x1E–0x1F
PKTS2
0
1
0
0
0
0
1
INPPF1
R/W
R/W
0
0
1
1
7
0
0
7
0
0
Number of committed packets + current packet bytes
Current packet bytes only
EP4PF
R/W
R/W
6
0
0
6
0
PKTS1
0
0
1
1
0
EP4EF
R/W
R/W
5
0
0
5
0
PF applies to
INPPF0
0
1
0
1
EP4FF
R/W
R/W
4
0
0
4
0
PKTS0
0
1
0
1
0
R/W
R/W
3
0
0
3
0
0
INPPF2
EP2PF
R/W
R/W
2
0
2
0
Number of packets
1 (default)
Packets
Invalid
EPnPFH:L format
INPPF1
EP4EF
2
3
PKTS[] PFC[]
R/W
R/W
0
1
2
3
4
1
0
1
0
0x1A, 0x1B, 0x1C, 0x1D
PFC[]
CY7C68001
Page 27 of 50
INPPF0
EP4FF
R/W
R/W
0
1
0
1
0x1E