DP83916VF National Semiconductor, DP83916VF Datasheet - Page 89

• Manufacturer Part Number: DP83916VF
• Description: IC CTRLR ORIENT NETWK IN 132PQFP
• Manufacturer: National Semiconductor
• Series: SONIC™r

Specifications of DP83916VF

• Controller Type: Network Interface Controller (NIC)
• Interface: Bus
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Voltage - Supply: -
• Operating Temperature: -
• Other names: *DP83916VF

7 0 AC and DC Specifications
REGISTER WRITE BMODE
Note 1 This figure shows a slave access to the SONIC-16 when the SONIC-16 is idle or rather not in master mode If the SONIC-16 is a bus master there will be
some differences as noted in the Memory Arbitration Slave Access diagram The BSCK states (T1 T2 etc ) are the equivalent processor states during a slave
access
Note 2 If CS is deasserted before the rising edge of SAS then T77 is referenced off the rising edge of CS instead of SAS
Note 3 DSACK0 1 are driven high for about
Note 4 bcyc
Note 5 It is not necessary to meet the setup time for CS since this signal is asynchronously sampled Meeting the setup time for this signal however makes it
possible to use T60 to determine exactly when SMACK will be asserted
Note 6 The smaller value for T60 refers to when the SONIC-16 is accessed during an Idle condition and the other value refers to when the SONIC-16 is accessed
during non-idle conditions These values are not tested but are guaranteed by design This specification assumes that CS is asserted
falling edge that CS is asynchronously clocked in on (see T56) If T56 is met for CS then SMACK will be asserted exactly 1 bus clock when the SONIC-16 was idle
or 5 bus clocks when the SONIC-16 was in master mode after the edge that T56 refers to (This is assuming that there were no wait states in the current master
mode access Wait states will increase the time for SMACK to go low by the number of wait states in the cycle )
Note 7 SAS may be asserted low anytime before or simultaneous to the falling edge of CS
Note 8 These values are not tested but are guaranteed by design They are provided as a design guideline only
Number
T56
T60
T62
T63
T66
T70a
T71a
T72a
T75b
T77
T77a
T78
T79a
T81
T83
T84
T85a
e
bus clock cycle time (T3)
CS Asynch Setup to BSCK (Note 5)
MREQ or CS to SMACK Low (Notes 4 6 8)
SAS Assertion before CS (Note 7)
Register Address Setup to SAS
Register Address Hold from SAS
SRW (Write) Setup to SAS
SRW (Write) Hold from SAS
SMACK to DSACK0 1 Low (Notes 4 8)
BSCK to DSACK0 1 Low
CS to DSACK0 1 High (Notes 2 3)
SAS to DSACK0 1 High (Notes 2 3)
Skew between DSACK0 1
BSCK to SMACK High
BSCK to SMACK Low
Register Write Data Setup to BSCK
Register Write Data Hold from BSCK
Min CS Deassert Time (Note 4)
e
1 (Note 1)
bus clock before going TRI-STATE
Parameter
(Continued)
89
Min
12
10
10
10
45
20
0
0
1
20 MHz
2
Max
1 5
5 5
44
25
35
10
30
25
bus clock before the
TL F 11722 – 76
Units
bcyc
bcyc
bcyc
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns