DP83916VF National Semiconductor, DP83916VF Datasheet - Page 49

• Manufacturer Part Number: DP83916VF
• Description: IC CTRLR ORIENT NETWK IN 132PQFP
• Manufacturer: National Semiconductor
• Series: SONIC™r

Specifications of DP83916VF

• Controller Type: Network Interface Controller (NIC)
• Interface: Bus
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Voltage - Supply: -
• Operating Temperature: -
• Other names: *DP83916VF

BUS INTERFACE PINS (Continued)
CS
SAS
SDS
SRW
SWR
DS
DSACK0
RDYi
DSACK1
RDYo
BRT
ECS
5 0 Bus Interface
Symbol
Driver
Type
TRI
TRI
TRI
TRI
TRI
Direction
(Continued)
I O Z
I O Z
O Z
O Z
O Z
I
I
I
I
I
I
I
Chip Select The system asserts this pin low to access the SONIC-16’s registers The
registers are selected by placing an address on lines RA5– RA0
Note Both CS and MREQ must not be asserted concurrently If these signals are
successively asserted there must be at least two bus clocks between the deasserting
edge of the first signal and the asserting edge of the second signal
Slave Address Strobe The system asserts this pin to latch the register address on
lines RA0– RA5 When BMODE
When BMODE
Slave Data Strobe The system asserts this pin to indicate valid data is on the bus
during a register write operation or when data may be driven onto the bus during a
register read operation
The system asserts this pin to indicate whether it will read from or write to the SONIC-
16’s registers
Slave Read Write (SRW) When BMODE
read and low during a write
Slave Read Write Strobe (SWR) when BMODE
a read and high during a write
Data Strobe When the SONIC-16 is bus master it drives this pin low during a read
cycle to indicate that the slave device may drive data onto the bus in a write cycle this
pin indicates that the SONIC-16 has placed valid data onto the bus
Data and Size Acknowledge 0 and 1 (DSACK0 1 BMODE
output slave acknowledge to the system when the SONIC-16 registers have been
accessed and the input slave acknowledgement when the SONIC-16 is busmaster
When a register has been accessed the SONIC-16 drives the DSACK0 1 pins low to
terminate the slave cycle (Note that the SONIC-16 responds as a 32-bit peripheral but
drives data only on lines D0– D15) When the SONIC-16 is bus master it samples these
pins before terminating its memory cycle These pins are sampled synchronously or
asynchronously depending on the state of the SBUS bit in the Data Configuration
register See Section 5 4 5 for details Note that the SONIC-16 does not allow dynamic
bus sizing
Ready Input (RDYi BMODE
asserts this signal high to insert wait-states and low to terminate the memory cycle This
signal is sampled synchronously or asynchronously depending on the state of the SBUS
bit See Sections 5 4 5 and 4 3 2 for details
Ready Output (RDYo BMODE
asserts this signal to terminate the slave cycle
Bus Retry When the SONIC-16 is bus master the system asserts this signal to rectify a
potentially correctable bus error This pin has 2 modes Mode 1 (the LBR in the Data
Configuration register is set to 0) Assertion of this pin forces the SONIC-16 to terminate
the current bus cycle and will repeat the same cycle after BRT has been deasserted
Mode 2 (the LBR bit in the Data Configuration register is set to 1) Assertion of this
signal forces the SONIC-16 to retry the bus operation as in Mode 1 However the
SONIC-16 will not continue DMA operations until the BR bit in the ISR is reset
Early Cycle Start This output gives the system earliest indication that a memory
operation is occurring This signal is driven low at the rising edge of T1 and high at the
falling edge of T1
TABLE 5-1 Pin Description (Continued)
e
0 the address is latched on the rising edge of SAS
49
e
e
0) When the SONIC-16 is a bus master the system
e
1 the address is latched on the falling edge of SAS
0) When a register is accessed the SONIC-16
Description
e
1 this signal is asserted high during a
e
0 this signal is asserted low during
e
1) These pins are the