DP83916VF National Semiconductor, DP83916VF Datasheet - Page 57

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DP83916VF

Manufacturer Part Number
DP83916VF
Description
IC CTRLR ORIENT NETWK IN 132PQFP
Manufacturer
National Semiconductor
Series
SONIC™r
Datasheet

Specifications of DP83916VF

Controller Type
Network Interface Controller (NIC)
Interface
Bus
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Current - Supply
-
Voltage - Supply
-
Operating Temperature
-
Other names
*DP83916VF

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National
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5 0 Bus Interface
5 4 5 2 Memory Cycle for BMODE
Mode
On the rising edge of T1 the SONIC-16 asserts ECS to
indicate that the memory cycle is starting The address
(A31 –A1) bus status (S2–S0) and the direction strobe
(MRW) are driven and do not change for the remainder of
the memory cycle On the falling edge of T1 the SONIC-16
deasserts ECS and asserts AS
In synchronous mode DSACK0 1 are sampled on the rising
edge of T2 T2 states will be repeated until DSACK0 1 are
FIGURE 5-8 Memory Read BMODE
FIGURE 5-9 Memory Write BMODE
(Continued)
e
1 Synchronous
57
e
e
sampled properly in a low state DSACK0 1 must meet the
setup and hold times with respect to the rising edge of bus
clock for proper operation
During read cycles ( Figure 5-8 ) data (D15– D0) is latched at
the falling edge of T2 and DS is asserted at the falling edge
of T1 For write cycles ( Figure 5-9 ) data is driven on the
falling edge of T1 If there are wait states inserted DS is
asserted on the falling edge of T2 The SONIC-16 termi-
nates the memory cycle by deasserting AS and DS at the
falling edge of T2
1 Synchronous (1 Wait-State)
1 Synchronous (1 Wait-State)
TL F 11722 – 31
TL F 11722 – 33

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