DP83916VF National Semiconductor, DP83916VF Datasheet - Page 5

• Manufacturer Part Number: DP83916VF
• Description: IC CTRLR ORIENT NETWK IN 132PQFP
• Manufacturer: National Semiconductor
• Series: SONIC™r

Specifications of DP83916VF

• Controller Type: Network Interface Controller (NIC)
• Interface: Bus
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Voltage - Supply: -
• Operating Temperature: -
• Other names: *DP83916VF

1 0 Functional Description
network The ENDEC section detects this when its collision
receiver detects a 10 MHz signal on the differential collision
input pair The ENDEC also provides both the receive and
transmit clocks to the MAC unit The transmit clock is one
half of the oscillator input The receive clock is extracted
from the input data by the PLL
Oscillator The oscillator generates the 10 MHz transmit
clock signal for network timing The oscillator is controlled
by a parallel resonant crystal or by an external clock (see
section 6 1 3) The 20 MHz output of the oscillator is divided
by 2 to generate the 10 MHz transmit clock (TXC) for the
MAC section The oscillator provides an internal clock signal
for the encoding and decoding circuits
The signals provided to the MAC unit from the on-chip EN-
DEC are also provided as outputs to the user
Loopback Functions The SONIC-16 provides three loop-
back modes These modes allow loopback testing at the
MAC ENDEC and external transceiver level (see section
1 7 for details) It is important to note that when the SONIC-
16 is transmitting the transmitted packet will always be
looped back by the external transceiver The SONIC-16
takes advantage of this to monitor the transmitted packet
See the explanation of the Receive State Machine in sec-
tion 1 2 1 for more information about monitoring transmitted
packets
1 1 2 Selecting An External ENDEC
An option is provided on SONIC-16 to disable the on-chip
ENDEC unit and use an external ENDEC The internal IEEE
802 3 ENDEC can be bypassed by connecting the EXT pin
to V
ed out from the chip allowing an external ENDEC to be
used See section 5 2 for the alternate pin definitions
1 2 MAC UNIT
The MAC (Media Access Control) unit performs the media
access control functions for transmitting and receiving pack-
ets over Ethernet During transmission the MAC unit frames
information from the transmit FIFO and supplies serialized
data to the ENDEC unit During reception the incoming in-
formation from the ENDEC unit is deserialized the frame
checked for valid reception and the data is transferred to
the receive FIFO Control and status registers on the
SONIC-16 govern the operation of the MAC unit
1 2 1 MAC Receive Section
The receive section (Figure 1-3 ) controls the MAC receive
operations during reception loopback and transmission
During reception the deserializer goes active after detecting
the 2-bit SFD (Start of Frame Delimiter) pattern (section
2 1) It then frames the incoming bits into octet boundaries
CC
(EXT
e
1) In this mode the MAC signals are redirect-
(Continued)
FIGURE 1-3 MAC Receiver
5
and transfers the data to the 32-byte receive FIFO Concur-
rently the address comparator compares the Destination
Address Field to the addresses stored in the chip’s CAM
address registers (Content Addressable Memory cells) If a
match occurs the deserializer passes the remainder of the
packet to the receive FIFO The packet is decapsulated
when the carrier sense input pin (CRS) goes inactive At the
end of reception the receive section checks the following
The appropriate status is indicated in the Receive Control
register (section 4 3 3) In loopback operations the receive
section operates the same as during normal reception
During transmission the receive section remains active to
allow monitoring of the self-received packet The CRC
checker operates as normal and the Source Address field
is compared with the CAM address entries Status of the
CRC check and the source address comparison is indicated
by the PMB bit in the Transmit Control register (section
4 3 4) No data is written to the receive FIFO during transmit
operations
The receive section consists of the following blocks detailed
below
Receive State Machine (RSM) The RSM insures the prop-
er sequencing for normal reception and self-reception dur-
ing transmission When the network is inactive the RSM
remains in an idle state continually monitoring for network
activity If the network becomes active the RSM allows the
deserializer to write data into the receive FIFO During this
state the following conditions may prevent the complete
reception of the packet
If these conditions do not occur the RSM processes the
packet indicating the appropriate status in the Receive Con-
trol register
Frame alignment errors
CRC errors
Length errors (runt packets)
FIFO Overrun The receive FIFO has been completely
filled before the SONIC-16 could buffer the data to mem-
ory
CAM Address Mismatch The packet is rejected be-
cause of a mismatch between the destination address of
the packet and the address in the CAM
Memory Resource Error There are no more resources
(buffers) available for buffering the incoming packets
Collision or Other Error A collision occured on the net-
work or some other error such as a CRC error occurred
(this is true if the SONIC-16 has been told to reject pack-
ets on a collision or reject packets with errors)
TL F 11722– 4