DP83916VF National Semiconductor, DP83916VF Datasheet - Page 81

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DP83916VF

Manufacturer Part Number
DP83916VF
Description
IC CTRLR ORIENT NETWK IN 132PQFP
Manufacturer
National Semiconductor
Series
SONIC™r
Datasheet

Specifications of DP83916VF

Controller Type
Network Interface Controller (NIC)
Interface
Bus
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Current - Supply
-
Voltage - Supply
-
Operating Temperature
-
Other names
*DP83916VF

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DP83916VF
Manufacturer:
National
Quantity:
226
Part Number:
DP83916VF
Manufacturer:
NS/国半
Quantity:
20 000
7 0 AC and DC Specifications
MEMORY READ BMODE
Note 1 For successive write operations MRW remains low
Note 2 Meeting the setup time for DSACK0 1 or STERM guarantees that the SONIC-16 will terminate the memory cycle 1
sampled or 1 cycle after STERM was sampled T2 states will be repeated until DSACK0 1 or STERM are sampled properly in a low state If the SONIC-16 samples
DSACK0 1 or STERM low during the T1 or first T2 state respectively the SONIC-16 will finish the current access in a total of two bus clocks instead of three
(assuming that programmable wait states are set to 0) DSACK0 1 are asynchronously sampled and STERM is synchronously sampled
Note 3 bcyc
Number
T9
T10
T11a
T12a
T13a
T14
T15a
T16
T17
T22
T23a
T24a
T28
T30
T30a
T31
T31a
e
bus clock cycle time (T3) bch
BSCK to Address Valid
Address Hold Time from BSCK
BSCK to AS DS ECS Low
BSCK to AS ECS High
BSCK to DS High
AS Strobe Low Width (Note 3)
AS Strobe High Width (Note 3)
Read Data Strobe High Width (Note 3)
Read Data Strobe Low Width (Note 3)
Address Valid to AS (Note 3)
Read Data Setup Time to BSCK
Read Data Hold Time from BSCK
BSCK to MRW (Read) Valid (Note 1)
DSACK0 1 Setup to BSCK (Note 2)
STERM Setup to BSCK (Note 2)
DSACK0 1 Hold from BSCK
STERM Hold from BSCK
e
1 ASYNCHRONOUS MODE
e
Parameter
bus clock high time (T2)
(Continued)
81
bcyc
bcyc
bch
bcyc
bcyc
Min
10
12
12
5
5
8
6
b
b
b
b
b
18
15
12
7
5
20 MHz
Max
bus clocks after DSACK0 1 were
34
26
34
36
30
TL F 11722 – 68
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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