DP83916VF National Semiconductor, DP83916VF Datasheet - Page 63

• Manufacturer Part Number: DP83916VF
• Description: IC CTRLR ORIENT NETWK IN 132PQFP
• Manufacturer: National Semiconductor
• Series: SONIC™r

Specifications of DP83916VF

• Controller Type: Network Interface Controller (NIC)
• Interface: Bus
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Voltage - Supply: -
• Operating Temperature: -
• Other names: *DP83916VF

5 0 Bus Interface
5 4 6 Bus Exceptions (Bus Retry)
The SONIC-16 provides the capability of handling errors
during the execution of the bus cycle ( Figure 5-20 )
The system asserts BRT (bus retry) to force the SONIC-16
to repeat the current memory cycle When the SONIC-16
detects the assertion of BRT it completes the memory cy-
cle at the end of T2 and gets off the bus by deasserting
BGACK or HOLD Then if Latched Bus Retry mode is not
set (LBR in the Data Configuration Register Section 4 3 2)
the SONIC-16 requests the bus again to retry the same
memory cycle If Latched Bus Retry is set though the SON-
IC-16 will not retry until the BR bit in the ISR (see Section
4 3 6) has been reset and BRT is deasserted BRT has
precedence of terminating a memory cycle over DSACK0 1
STERM or RDYi
BRT may be sampled synchronously or asynchronously by
setting the EXBUS bit in the DCR (see Section 4 3 2) If
synchronous Bus Retry is set BRT is sampled on the rising
edge of T2 If asynchronous Bus Retry is set BRT is double
synchronized from the falling edge of T1 The asynchronous
setup time does not need to be met but doing so will guar-
antee that the bus exception will occur in the current bus
cycle instead of the next bus cycle Asynchronous Bus Re-
try may only be used when the SONIC-16 is set to asynchro-
nous mode
Note 1 The deassertion edge of HOLD is dependent on the PH bit in the
Note 2 If Latched Bus retry is set BRT need only satisfy its setup time (the
Note 3 If DSACK0 1 STERM or RDYi remain asserted after BRT the next
5 4 7 Slave Mode Bus Cycle
The SONIC-16’s internal registers can be accessed by one
of two methods (BMODE
methods the SONIC-16 is a slave on the bus This section
describes the SONIC-16’s slave mode bus operations
5 4 7 1 Slave Cycle for BMODE
The system accesses the SONIC-16 by driving SAS SRW
and RA
cle but the SONIC-16 will not actually start a slave cycle
until CS has also been asserted CS should not be asserted
before SAS is driven low as this will cause improper slave
DCR2 (see Section 4 3 7) Also BGACK is driven high for about
bus clock before going TRI-STATE
hold time is not important) Otherwise BRT must remain asserted
until after the Th state
memory cycle may be adversely affected
k
5 0
l
These signals will be sampled each bus cy-
e
(Continued)
1 or BMODE
e
1
FIGURE 5-20 Bus Exception (Bus Retry)
e
0) In both
63
operation Once SAS has been driven low between one
and two bus clocks after the assertion of CS SMACK will be
asserted to signify that the SONIC-16 has started the slave
cycle Although CS is an asynchronous input meeting its
setup time (as shown in Figures 5-21 and 5-22 ) will guaran-
tee that SMACK which is asserted off of a falling edge will
be asserted 1 bus clock after the falling edge that CS is
clocked in on This is assuming that the SONIC-16 is not a
bus master when CS was asserted If the SONIC-16 is a bus
master then when CS is asserted the SONIC-16 will com-
plete its current master bus cycle and get off the bus tempo-
rarily (see Section 5 4 8) In this case SMACK will be as-
serted 5 bus clocks after the falling edge that CS was
clocked in on This is assuming that there were no wait
states in the current master mode access Wait states will
increase the time for SMACK to go low by the number of
wait states in the cycle
If the slave access is a read cycle ( Figure 5-21 ) then the
data will be driven off the same edge as SMACK If it is a
write cycle ( Figure 5-22 ) then the data will be latched in
exactly 2 bus clocks after the assertion of SMACK In either
case DSACK0 1 are driven low 2 bus clocks after SMACK
to terminate the slave cycle For a read cycle the assertion
of DSACK0 1 indicates valid register data and for a write
cycle the assertion indicates that the SONIC-16 has
latched the data The SONIC-16 deasserts DSACK0 1
SMACK and the data if the cycle is a read cycle at the rising
edge of SAS or CS depending on which is deasserted first
Note 1 Although the SONIC-16 responds as a 32-bit peripheral when it
Note 2 For multiple register accesses CS can be held low and SAS can be
Note 3 If memory request (MREQ) follows a chip select (CS) it must be
Note 4 When CS is deasserted it must remain deasserted for at least one
Note 5 The way in which SMACK is asserted due to CS is not the same as
drives DSACK0 1 low it transfers data only on lines D
used to delimit the slave cycle (this is the only case where CS may
be asserted before SAS) In this case SMACK will be driven low
due to SAS going low since CS has already been asserted Notice
that this means SMACK will not stay asserted low during the entire
time CS is low (as is the case for MREQ Section 5 4 8)
asserted at least 2 bus clocks after CS is deasserted Both CS and
MREQ must not be asserted concurrently
bus clock
the way in which SMACK is asserted due to MREQ The assertion
of SMACK is dependent upon both CS and SAS being low not just
CS This is not the same as the case for MREQ (see Section 5 4 8)
The assertion of SMACK in these two cases should not be con-
fused
TL F 11722 – 46
k
15 0
l