DP83916VF National Semiconductor, DP83916VF Datasheet - Page 85

• Manufacturer Part Number: DP83916VF
• Description: IC CTRLR ORIENT NETWK IN 132PQFP
• Manufacturer: National Semiconductor
• Series: SONIC™r

Specifications of DP83916VF

• Controller Type: Network Interface Controller (NIC)
• Interface: Bus
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Voltage - Supply: -
• Operating Temperature: -
• Other names: *DP83916VF

7 0 AC and DC Specifications
MEMORY ARBITRATION SLAVE ACCESS
Note 1 Both CS and MREQ must not be asserted concurrently If these signals are successively asserted there must be at least two bus clocks between the
deasserting and asserting edges of these signals
Note 2 It is not necessary to meet the setup times for MREQ or CS since these signals are asynchronously sampled Meeting the setup time for these signals
however makes it possible to use T60 to determine exactly when SMACK will be asserted
Note 3 The smaller value for T60 refers to when the SONIC-16 is accessed during an Idle condition and the other value refers to when the SONIC-16 is accessed
during non-idle conditions These values are not tested but are guaranteed by design This specification assumes that CS or MREQ is asserted
the falling edge that these signals are asynchronously clocked in on (see T56 and T58) If T56 is met for CS or T58 is met for MREQ then SMACK will be asserted
exactly 1 bus clock when the SONIC-16 was idle or 5 bus clocks when the SONIC-16 was in master mode after the edge that T56 and T58 refer to (This is
assuming that there were no wait states in the current master mode access Wait states will increase the time for SMACK to go low by the number of wait states in
the cycle ) SAS must have been asserted for this timing to be correct See SAS and CS timing in the Register Read and Register Write timing specifications
Note 4 bcyc
Note 5 The way in which SMACK is asserted is due to CS is not the same as the way in which SMACK is asserted due to MREQ SMACK goes low as a direct
result of the assertion of MREQ whereas for CS SAS must also be driven low (BMODE
that when SMACK is asserted due to MREQ SMACK will remain asserted until MREQ is deasserted Multiple memory accesses can be made to the shared
memory without SMACK ever going high When SMACK is asserted due to CS however SMACK will only remain low as long as SAS is also low (BMODE
high (BMODE
an important difference to consider when designing shared memory designs
Number
T56
T57
T58
T59
T60
T80
T81
e
e
bus clock cycle time (T3)
0) SMACK will not remain low throughout multiple register accesses to the SONIC-16 because SAS must toggle for each register access This is
CS Low Asynch Setup to BSCK
(Note 2)
CS High Asynch Setup to BSCK
MREQ Low Asynch Setup to BSCK
(Note 2)
MREQ High Asynch Setup to BSCK
MREQ or CS to SMACK Low (Notes 3 4)
MREQ to SMACK High
BSCK to SMACK Low
Parameter
(Continued)
85
e
1) or high (BMODE
Min
12
12
12
8
e
20 MHz
0) before SMACK will be asserted This means
Max
1 5
5 5
30
25
bus clock before
TL F 11722 – 72
Units
bcyc
ns
ns
ns
ns
ns
ns
e
1) or