DP83916VF National Semiconductor, DP83916VF Datasheet - Page 59

• Manufacturer Part Number: DP83916VF
• Description: IC CTRLR ORIENT NETWK IN 132PQFP
• Manufacturer: National Semiconductor
• Series: SONIC™r

Specifications of DP83916VF

• Controller Type: Network Interface Controller (NIC)
• Interface: Bus
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Voltage - Supply: -
• Operating Temperature: -
• Other names: *DP83916VF

5 0 Bus Interface
bus clocks after DSACK0 1 were sampled or 1 cycle after
STERM was sampled T2 states will be repeated until
DSACK0 1 or STERM are sampled properly in a low state
(see note below)
During read cycles ( Figure 5-10 and 5-11 ) data (D15– D0) is
latched at the falling edge of T2 and DS is asserted at the
falling edge of T1 For write cycles ( Figures 5-12 and 5-13 )
data is driven on the falling edge of T1 If there are wait
FIGURE 5-12 Memory Write BMODE
FIGURE 5-13 Memory Write BMODE
(Continued)
59
e
e
states inserted DS is asserted on the falling edge of the first
T2(wait) DS is not asserted for zero wait state write cycles
The SONIC-16 terminates the memory cycle by deasserting
AS and DS at the falling edge of T2
Note If the setup time for DSACK0 1 is met during T1 or the setup time for
1 Asynchronous (1 Wait-State)
1 Asynchronous (2 Wait-State)
STERM is met during the first T2 the full asynchronous bus cycle will
take only 2 bus clocks This may be an unwanted situation If so
DSACK0 1 and STERM should be deasserted during T1 and the start
of T2 respectively
TL F 11722 – 34
TL F 11722 – 35