DS21Q42T+ Maxim Integrated Products, DS21Q42T+ Datasheet - Page 83

• Manufacturer Part Number: DS21Q42T+
• Description: IC FRAMER ENHANCED T1 4X 128TQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q42T+

• Controller Type: T1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 19-1. INSTRUCTION CODES FOR THE DS21352/552
IEEE 1149.1 ARCHITECTURE
SAMPLE/PRELOAD
BYPASS
EXTEST
CLAMP
HIGHZ
IDCODE
SAMPLE/PRELOAD
A mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions. The
digital I/Os of the DS21Q42 can be sampled at the boundary scan register without interfering with the
normal operation of the device by using the Capture-DR state. SAMPLE/PRELOAD also allows the
DS21Q42 to shift data into the boundary scan register via JTDI using the Shift-DR state.
EXTEST
EXTEST allows testing of all interconnections to the DS21Q42. When the EXTEST instruction is
latched in the instruction register, the following actions occur. Once enabled via the Update-IR state, the
parallel outputs of all digital output pins will be driven. The boundary scan register will be connected
between JTDI and JTDO. The Capture-DR will sample all digital inputs into the boundary scan register.
BYPASS
When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO
through the one-bit bypass test register. This allows data to pass from JTDI to JTDO not affecting the
device’s normal operation.
IDCODE
When the IDCODE instruction is latched into the parallel instruction register, the Identification Test
register is selected. The device identification code will be loaded into the Identification register on the
rising edge of JTCLK following entry into the Capture-DR state. Shift-DR can be used to shift the
identification code out serially via JTDO. During Test-Logic-Reset, the identification code is forced into
the instruction register’s parallel output. The ID code will always have a ‘1’ in the LSB position. The
next 11 bits identify the manufacturer’s JEDEC number and number of continuation bytes followed by 16
bits for the device and 4 bits for the version. See Table 19-2. Table 19-3 lists the device ID codes for the
DS21Q42 and DS21Q44 devices.
Table 19-2. ID CODE STRUCTURE
CONTENTS
LENGTH
INSTRUCTION
MSB
(Contact Factory)
Version
4 bits
Boundary Scan
Bypass
Boundary Scan
Bypass
Bypass
Device Identification
SELECTED REGISTER
(See Table 19-3)
Device ID
16bits
83 of 116
“00010100001”
JEDEC
11bits
INSTRUCTION CODES
LSB
010
111
000
011
100
001
1bit
“1”