DS21Q42T+ Maxim Integrated Products, DS21Q42T+ Datasheet - Page 79

• Manufacturer Part Number: DS21Q42T+
• Description: IC FRAMER ENHANCED T1 4X 128TQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q42T+

• Controller Type: T1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.
19.1 Description
The DS21Q42 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD,
BYPASS, and EXTEST. Optional public instructions included with this design are HIGHZ, CLAMP,
and IDCODE. See Figure 19-1 for a block diagram. The DS21Q42 contains the following items, which
meet the requirements, set by the IEEE 1149.1 Standard Test Access Port and Boundary Scan
Architecture.
Test Access Port (TAP)
TAP Controller
Instruction Register
Bypass Register
Boundary Scan Register
Device Identification Register
The JTAG feature is only available when the DS21Q42 feature set is selected (FMS = 0). The JTAG
feature is disabled when the DS21Q42 is configured for emulation of the DS21Q41B (FMS = 1). Details
on Boundary Scan Architecture and the Test Access Port can be found in IEEE 1149.1-1990, IEEE
1149.1a-1993, and IEEE 1149.1b-1994.
The Test Access Port has the necessary interface pins; JTRST, JTCLK, JTMS, JTDI, and JTDO. See the
pin descriptions for details.
Figure 19-1. BOUNDARY SCAN ARCHITECTURE
JTAG-BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT
10K
+V
JTDI
10K
+V
JTMS
Test Access Port
Boundary Scan
Identification
Instruction
Bypass
Register
Controller
Register
Register
Register
JTCLK
10K
+V
JTRST
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Select
Output Enable
MUX
JTDO