DS21Q42T+ Maxim Integrated Products, DS21Q42T+ Datasheet - Page 50

• Manufacturer Part Number: DS21Q42T+
• Description: IC FRAMER ENHANCED T1 4X 128TQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q42T+

• Controller Type: T1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RDS0M: RECEIVE DS0 MONITOR REGISTER (Address=1F Hex)
10.
Each framer in the DS21Q42 contains provisions for both processor based (i.e., software based) signaling
bit access and for hardware based access. Both the processor based access and the hardware based access
can be used simultaneously if necessary. The processor based signaling is covered in Section 10.1 and
the hardware based signaling is covered in Section 10.2.
10.1 Processor-Based Signaling
The robbed–bit signaling bits embedded in the T1 stream can be extracted from the receive stream and
inserted into the transmit stream by each framer. There is a set of 12 registers for the receive side (RS1 to
RS12) and 12 registers on the transmit side (TS1 to TS12). The signaling registers are detailed below.
The CCR1.5 bit is used to control the robbed signaling bits as they appear at RSER. If CCR1.5 is set to
zero, then the robbed signaling bits will appear at the RSER pin in their proper position as they are
received. If CCR1.5 is set to a one, then the robbed signaling bit positions will be forced to a one at
RSER. If hardware based signaling is being used, then CCR1.5 must be set to zero.
(MSB)
B1
SYMBOL
SYMBOL
RCM3
RCM2
RCM1
RCM0
SIGNALING OPERATION
B1
B2
B3
B4
B5
B6
B7
B8
B2
POSITION
POSITION
RDS0M.7
RDS0M.6
RDS0M.5
RDS0M.4
RDS0M.3
RDS0M.2
RDS0M.1
RDS0M.0
CCR6.3
CCR6.2
CCR6.1
CCR6.0
B3
NAME AND DESCRIPTION
Receive Channel Monitor Bit 3.
Receive Channel Monitor Bit 2.
Receive Channel Monitor Bit 1.
Receive Channel Monitor Bit 0. LSB of the channel decode.
NAME AND DESCRIPTION
Receive DS0 Channel Bit 1. MSB of the DS0 channel (first
bit to be received).
Receive DS0 Channel Bit 2.
Receive DS0 Channel Bit 3.
Receive DS0 Channel Bit 4.
Receive DS0 Channel Bit 5.
Receive DS0 Channel Bit 6.
Receive DS0 Channel Bit 7.
Receive DS0 Channel Bit 8. LSB of the DS0 channel (last bit
to be received).
B4
50 of 116
B5
B6
B7
(LSB)
B8