DS21Q42T+ Maxim Integrated Products, DS21Q42T+ Datasheet - Page 48

• Manufacturer Part Number: DS21Q42T+
• Description: IC FRAMER ENHANCED T1 4X 128TQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q42T+

• Controller Type: T1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 8-3. MULTIFRAMES OUT OF SYNC COUNTING ARRANGEMENTS
9. DS0 MONITORING FUNCTION
Each framer in the DS21Q42 has the ability to monitor one DS0 64 kbps channel in the transmit direction
and one DS0 channel in the receive direction at the same time. In the transmit direction the user will
determine which channel is to be monitored by properly setting the TCM0 to TCM4 bits in the CCR5
register. In the receive direction, the RCM0 to RCM4 bits in the CCR6 register need to be properly set.
The DS0 channel pointed to by the TCM0 to TCM4 bits will appear in the Transmit DS0 Monitor
(TDS0M) register and the DS0 channel pointed to by the RCM0 to RCM4 bits will appear in the Receive
DS0 (RDS0M) register. The TCM4 to TCM0 and RCM4 to RCM0 bits should be programmed with the
decimal decode of the appropriate T1 channel. For example, if DS0 channel 6 (timeslot 5) in the transmit
direction and DS0 channel 15 (timeslot 14) in the receive direction needed to be monitored, then the
following values would be programmed into CCR5 and CCR6:
CCR5: COMMON CONTROL REGISTER 5 (Address=19 Hex)
[repeated here from section 6 for convenience]
TDS0M: TRANSMIT DS0 MONITOR REGISTER (Address=1A Hex)
FRAMING MODE
(MSB)
TJC
SYMBOL
(CCR2.3)
TCM4
TCM3
TCM2
TCM1
TCM0
TCM4 = 0
TCM3 = 0
TCM2 = 1
TCM1 = 0
TCM0 = 1
TJC
ESF
ESF
D4
D4
–
–
–
RCM4 = 0
RCM3 = 1
RCM2 = 1
RCM1 = 1
RCM0 = 0
COUNT MOS OR F-BIT
POSITION
ERRORS (RCR2.0)
CCR5.7
CCR5.5
CCR5.5
CCR5.4
CCR5.3
CCR5.2
CCR5.1
CCR5.0
–
MOS
MOS
F-Bit
F-Bit
TCM4
NAME AND DESCRIPTION
Transmit Japanese CRC Enable. See Section 6 for details.
Not Assigned. Must be set to zero when written.
Not Assigned. Must be set to zero when written.
Transmit Channel Monitor Bit 4. MSB of a channel decode
that determines which transmit DS0 channel data will appear
in the TDS0M register.
Transmit Channel Monitor Bit 3.
Transmit Channel Monitor Bit 2.
Transmit Channel Monitor Bit 1.
Transmit Channel Monitor Bit 0. LSB of the channel
decode that determines which transmit DS0 channel data will
appear in the TDS0M register.
48 of 116
Number of multiframes out of sync
Number of multiframes out of sync
Errors in the FPS pattern
Errors in the Ft pattern
TCM3
WHAT IS COUNTED IN THE MOSCRs
TCM2
TCM1
TCM0
(LSB)