DS21Q42T+ Maxim Integrated Products, DS21Q42T+ Datasheet - Page 71

• Manufacturer Part Number: DS21Q42T+
• Description: IC FRAMER ENHANCED T1 4X 128TQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q42T+

• Controller Type: T1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.2. Legacy FDL Support
15.2.1 Overview
The DS21Q42 maintains the circuitry that existed in the previous generation of Dallas Semiconductor’s
single chip transceivers and quad framers. Section 15.2 covers the circuitry and operation of this legacy
functionality. In new applications, it is recommended that the HDLC controller and BOC controller
described in Section 15.1 be used. On the receive side, it is possible to have both the new HDLC/BOC
controller and the legacy hardware working at the same time. However this is not possible on the
transmit side since their can be only one source the of the FDL data internal to the device.
15.2.2 Receive Section
In the receive section, the recovered FDL bits or Fs bits are shifted bit–by–bit into the Receive FDL
register (RFDL). Since the RFDL is 8 bits in length, it will fill up every 2 ms (8 times 250 us). The
framer will signal an external microcontroller that the buffer has filled via the SR2.4 bit. If enabled via
IMR2.4, the INT* pin will toggle low indicating that the buffer has filled and needs to be read. The user
has 2 ms to read this data before it is lost. If the byte in the RFDL matches either of the bytes
programmed into the RMTCH1 or RMTCH2 registers, then the SR2.2 bit will be set to a one and the
INT* pin will toggled low if enabled via IMR2.2. This feature allows an external microcontroller to
ignore the FDL or Fs pattern until an important event occurs.
The framer also contains a zero destuffer, which is controlled via the CCR2.0 bit. In both ANSI T1.403
and TR54016, communications on the FDL follows a subset of a LAPD protocol. The LAPD protocol
states that no more than 5 ones should be transmitted in a row so that the data does not resemble an
opening or closing flag (01111110) or an abort signal (11111111). If enabled via CCR2.0, the DS21Q42
will automatically look for 5 ones in a row, followed by a zero. If it finds such a pattern, it will
automatically remove the zero. If the zero destuffer sees six or more ones in a row followed by a zero,
the zero is not removed. The CCR2.0 bit should always be set to a one when the DS21Q42 is extracting
the FDL. More on how to use the DS21Q42 in FDL applications in this legacy support mode is covered
in a separate Application Note.
RFDL: RECEIVE FDL REGISTER (Address = 28 Hex)
(MSB)
RFDL7
The Receive FDL Register (RFDL) reports the incoming Facility Data Link (FDL) or the incoming Fs
bits. The LSB is received first.
SYMBOL
RFDL7
RFDL0
RFDL6
POSITION
RFDL.7
RFDL.0
RFDL5
RFDL4
NAME AND DESCRIPTION
MSB of the Received FDL Code
LSB of the Received FDL Code
71 of 116
RFDL3
RFDL2
RFDL1
(LSB)
RFDL0