DS21Q42T+ Maxim Integrated Products, DS21Q42T+ Datasheet - Page 34

• Manufacturer Part Number: DS21Q42T+
• Description: IC FRAMER ENHANCED T1 4X 128TQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q42T+

• Controller Type: T1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pulse Density Enforcer
The Framer always examines both the transmit and receive data streams for violations of the following
rules which are required by ANSI T1.403:
– No more than 15 consecutive zeros
– At least N ones in each and every time window of 8 x (N +1) bits where N = 1 through 23
Violations for the transmit and receive data streams are reported in the RIR2.0 and RIR2.1 bits
respectively. When the CCR3.3 is set to one, the DS21Q42 will force the transmitted stream to meet this
requirement no matter the content of the transmitted stream. When running B8ZS, the CCR3.3 bit should
be set to zero since B8ZS encoded data streams cannot violate the pulse density requirements.
CCR4: COMMON CONTROL REGISTER 4 (Address=11 Hex)
(MSB)
RSRE
SYMBOL
RFSA1
RPCSI
RSRE
RFE
RFF
RPCSI
POSITION
CCR4.7
CCR4.6
CCR4.5
CCR4.4
CCR4.3
RFSA1
NAME AND DESCRIPTION
Receive Side Signaling Re–Insertion Enable. See Section 10 for
details.
0 = do not re–insert signaling bits into the data stream presented at
the RSER pin
1 = reinsert the signaling bits into data stream presented at the
RSER pin
Receive Per–Channel Signaling Insert. See Section 10 for more
details.
0 = do not use RCHBLK to determine which channels should have
signaling re–inserted
1 = use RCHBLK to determine which channels should have
signaling re–inserted
Receive Force Signaling All Ones. See Section 10 for more
details.
0 = do not force extracted robbed–bit signaling bit positions to a one
1 = force extracted robbed–bit signaling bit positions to a one
Receive Freeze Enable. See Section 10 for details.
0 = no freezing of receive signaling data will occur
1 = allow freezing of receive signaling data at RSIG (and RSER if
CCR4.7 = 1).
Receive Force Freeze. Freezes receive side signaling at RSIG (and
RSER if CCR4.7=1); will override Receive Freeze Enable (RFE).
See Section 10 for details.
0 = do not force a freeze event
1 = force a freeze event
RFE
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RFF
THSE
TPCSI
(LSB)
TIRFS