DS21Q42T+ Maxim Integrated Products, DS21Q42T+ Datasheet - Page 72

• Manufacturer Part Number: DS21Q42T+
• Description: IC FRAMER ENHANCED T1 4X 128TQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q42T+

• Controller Type: T1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RMTCH1: RECEIVE FDL MATCH REGISTER 1 (Address = 29 Hex)
RMTCH2: RECEIVE FDL MATCH REGISTER 2 (Address = 2A Hex)
When the byte in the Receive FDL Register matches either of the two Receive FDL Match Registers
(RMTCH1/RMTCH2), SR2.2 will be set to a one and the INT* will go active if enabled via IMR2.2.
15.2.3 Transmit Section
The transmit section will shift out into the T1 data stream, either the FDL (in the ESF framing mode) or
the Fs bits (in the D4 framing mode) contained in the Transmit FDL register (TFDL). When a new value
is written to the TFDL, it will be multiplexed serially (LSB first) into the proper position in the outgoing
T1 data stream.
microcontroller that the buffer is empty and that more data is needed by setting the SR2.3 bit to a one.
The INT* will also toggle low if enabled via IMR2.3. The user has 2 ms to update the TFDL with a new
value. If the TFDL is not updated, the old value in the TFDL will be transmitted once again. The framer
also contains a zero stuffer, which is controlled via the CCR2.4 bit. In both ANSI T1.403 and TR54016,
communications on the FDL follows a subset of a LAPD protocol. The LAPD protocol states that no
more than 5 ones should be transmitted in a row so that the data does not resemble an opening or closing
flag (01111110) or an abort signal (11111111). If enabled via CCR2.4, the framer will automatically
look for 5 ones in a row. If it finds such a pattern, it will automatically insert a zero after the five ones.
The CCR2.0 bit should always be set to a one when the framer is inserting the FDL. More on how to use
the DS21Q42 in FDL applications is covered in a separate Application Note.
TFDL: TRANSMIT FDL REGISTER (Address = 7E Hex)
[Also used to insert Fs framing pattern in D4 framing mode; see Section 15.3]
The Transmit FDL Register (TFDL) contains the Facility Data Link (FDL) information that is to be
inserted on a byte basis into the outgoing T1 data stream. The LSB is transmitted first.
RMFDL7
TFDL7
(MSB)
(MSB)
SYMBOL
SYMBOL
RMFDL7
RMFDL0
TFDL7
TFDL0
RMFDL6
TFDL6
After the full eight bits has been shifted out, the framer will signal the host
POSITION
POSITION
RMTCH1.7
RMTCH2.7
RMTCH1.0
RMTCH2.0
TFDL.7
TFDL.0
RMFDL5
TFDL5
RMFDL4
NAME AND DESCRIPTION
MSB of the FDL Match Code
LSB of the FDL Match Code
NAME AND DESCRIPTION
MSB of the FDL code to be transmitted
LSB of the FDL code to be transmitted
TFDL4
72 of 116
RMFDL3
TFDL3
RMFDL2
TFDL2
RMFDL1
TFDL1
RMFDL0
TFDL0
(LSB)
(LSB)