DS21Q42T+ Maxim Integrated Products, DS21Q42T+ Datasheet - Page 63

• Manufacturer Part Number: DS21Q42T+
• Description: IC FRAMER ENHANCED T1 4X 128TQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q42T+

• Controller Type: T1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Transmit a HDLC Message
1) Make sure HDLC controller is done sending any previous messages and is current sending flags by
2) Enable either the THALF or TNF interrupt.
3) Read THIR to obtain TFULL status.
4) Repeat Step 3.
5) Wait for interrupt, skip to Step 3.
6) Disable THALF or TNF interrupt and enable TMEND interrupt.
7) Wait for an interrupt, then read TUDR status bit to make sure packet was transmitted correctly.
Transmit a BOC
1) Write 6-bit code into TBOC.
2) Set SBOC bit in TBOC = 1.
15.1.3 HDLC/BOC Register Description
HCR: HDLC CONTROL REGISTER (Address = 00 Hex)
(MSB)
RBR
checking that the FIFO is empty by reading the TEMPTY status bit in the THIR register.
a) If TFULL = 0, then write a byte into the FIFO and skip to next step (special case occurs when the
b) If TFULL = 1, then skip to Step 5.
SYMBOL
TEOM
TABT
RBR
RHR
THR
TFS
last byte is to be written; in this case, set TEOM = 1 before writing the byte and then skip to Step
6).
RHR
POSITION
HCR.7
HCR.6
HCR.5
HCR.4
HCR.3
HCR.2
TFS
THR
NAME AND DESCRIPTION
Receive BOC Reset. A 0 to 1 transition will reset the BOC
circuitry. Must be cleared and set again for a subsequent reset.
Receive HDLC Reset. A 0 to 1 transition will reset the HDLC
controller. Must be cleared and set again for a subsequent reset.
Transmit Flag/Idle Select.
0 = 7Eh
1 = FFh
Transmit HDLC/BOC Reset. A 0 to 1 transition will reset
both the HDLC controller and the transmit BOC circuitry.
Must be cleared and set again for a subsequent reset.
Transmit Abort. A 0 to 1 transition will cause the FIFO
contents to be dumped and one FEh abort to be sent followed
by 7Eh or FFh flags/idle until a new packet is initiated by
writing new data into the FIFO. Must be cleared and set again
for a subsequent abort to be sent.
Transmit End of Message. Should be set to a one just before
the last data byte of a HDLC packet is written into the transmit
FIFO at THFR. The HDLC controller will clear this bit when
the last byte has been transmitted.
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TABT
TEOM
TZSD
(LSB)
TCRCD