DS21Q42T+ Maxim Integrated Products, DS21Q42T+ Datasheet - Page 45
![IC FRAMER ENHANCED T1 4X 128TQFP](/photos/6/82/68247/128-lqfp_21-0086d_sml.jpg)
DS21Q42T+
Manufacturer Part Number
DS21Q42T+
Description
IC FRAMER ENHANCED T1 4X 128TQFP
Manufacturer
Maxim Integrated Products
Datasheet
1.DS21Q42T.pdf
(116 pages)
Specifications of DS21Q42T+
Controller Type
T1 Framer
Interface
Parallel/Serial
Voltage - Supply
2.97 V ~ 3.63 V
Current - Supply
75mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
128-TQFP, 128-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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- Download datasheet (950Kb)
8. ERROR COUNT REGISTERS
There are a set of three counters in each framer that record bipolar violations, excessive zeros, errors in
the CRC6 code words, framing bit errors, and number of multiframes that the device is out of receive
synchronization. Each of these three counters are automatically updated on either one second boundaries
(CCR3.2=0) or every 42 ms (CCR3.2=1) as determined by the timer in Status Register 2 (SR2.5). Hence,
these registers contain performance data from either the previous second or the previous 42 ms. The user
can use the interrupt from the one second timer to determine when to read these registers. The user has a
full second (or 42 ms) to read the counters before the data is lost. All three counters will saturate at their
respective maximum counts and they will not rollover (note: only the Line Code Violation Count Register
has the potential to overflow but the bit error would have to exceed 10
Line Code Violation Count Register (LCVCR)
Line Code Violation Count Register 1 (LCVCR1) is the most significant word and LCVCR2 is the least
significant word of a 16–bit counter that records code violations (CVs). CVs are defined as Bipolar
Violations (BPVs) or excessive zeros. See Table 8-1 for details of exactly what the LCVCRs count. If
the B8ZS mode is set for the receive side via CCR2.2, then B8ZS code words are not counted. This
counter is always enabled; it is not disabled during receive loss of synchronization (RLOS=1) conditions.
LCVCR1: LINE CODE VIOLATION COUNT REGISTER 1 (Address = 23 Hex)
LCVCR2: LINE CODE VIOLATION COUNT REGISTER 2 (Address = 24 Hex)
Table 8-1. LINE CODE VIOLATION COUNTING ARRANGEMENTS
COUNT EXCESSIVE 0’S?
LCV15
(MSB)
LCV7
SYMBOL
LCV15
LCV0
(RCR1.7)
LCV14
yes
yes
LCV6
no
no
LCV13
POSITION
LCV5
LCVCR1.7
LCVCR2.0
B8ZS ENABLED?
LCV12
LCV4
(CCR2.2)
yes
yes
no
no
NAME AND DESCRIPTION
MSB of the 16–bit code violation count
LSB of the 16–bit code violation count
LCV11
LCV3
45 of 116
BPVs
BPVs + 16 consecutive zeros
BPVs (B8ZS code words not
counted)
BPV’s + 8 consecutive zeros
WHAT IS COUNTED IN THE
LCV10
LCV2
-2
before this would occur).
LCVCRs
LCV9
LCV1
(LSB)
LCV8
LCV0
LCVCR1
LCVCR2
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