IDTSTAC9758XXTAEB1XR IDT, Integrated Device Technology Inc, IDTSTAC9758XXTAEB1XR Datasheet - Page 80

• Manufacturer Part Number: IDTSTAC9758XXTAEB1XR
• Description: IC CODEC AC'97 6CH 2.3 48-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Audio Codec '97r

Specifications of IDTSTAC9758XXTAEB1XR

• Data Interface: Serial
• Resolution (bits): 20 b
• Number Of Adcs / Dacs: 2 / 3
• Sigma Delta: Yes
• Voltage - Supply, Analog: 3.14 V ~ 3.47 V; 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 3.135V
• Single Supply Voltage (max): 3.465/5.25V
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: STAC9758XXTAEB1XR

IDT™
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
STAC9758/9759
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
Bit(s) Reset Value R/W
13:12
10:4
15
14
11
3
2
1
0
10
0
0
0
0
0
0
0
0
RW
RW
RW SPSR[1,0]
RW
RW
RW
RW
RW
RW
CC[6, 0]
/AUDIO
Name
COPY
DRS
PRE
PRO
V
L
Validity: This bit affects the "Validity" flag, bit[28] transmitted in each SPDIF
subframe, and enables the SPDIF transmitter to maintain connection during
error or mute conditions. Subframe bit[28] = 0 indicates that data is valid for
conversion at the receiver, 1 indicates invalid data (not suitable for
conversion at the receiver).
If "V" = 1, then each SPDIF subframe (Left & Right) should have bit[28]
"Validity" flag = 1 or set based on the assertion or de-assertion of the AC '97
"VFORCE" bit within the Extended Audio Status and Control Register (D15,
register 2Ah).
Double Rate SPDIF
0 = not enabled
1 = enables SPDIF Sample Rates of 64 KHz, 88.2 KHz, and 96 KHz
When DRS is enabled, the SPDIF transmitter uses AC-Link slots 3&4 plus
the slot pair specified in the SPSA bits (Reg 2A, Bits D5:D4) to supply data at
Fs=64KHz, 88.2KHz or 96KHz. A total of four slots are used for a stereo
pair when operating in this mode. The first stereo pair to be played is
contained in slots 3&4, and the second pair is contained in the slots specified
by the SPSA bits.
The SPCV bit must indicate a valid configuration. The STAC9758/9759
automatically determines the correct channel status bits for Fs from DRS and
SPSR and inserts them as necessary. The Controller or Driver should
perform write followed by read to determine if DRS is supported.
SPDIF and ADAT Sample Rate:
00 - 44.1KHz Rate
01 - Reserved
10 - 48KHz Rate (default)
11 - 32KHz Rate
When DRS (D14 is set), SPDIF (but not ADAT) will operate at:
00 - 88.2KHz
01 - Reserved
10 - 96 KHz (default)
11 - 64KHz
Generation Level is defined by the IEC standard, or as appropriate.
Category Code is defined by the IEC standard or as appropriate by media.
0 = 0 sec Pre-emphasis
1 = Pre-emphasis is 50/15 sec
0 = Copyright not asserted
1 = Copyright is asserted
0 = PCM data
1 = Non-Audio or non-PCM format
0 = Consumer use of the channel
1 = Professional use of the channel
80
Description
STAC9758/9759
PC AUDIO
V 1.2 1206