IDTSTAC9758XXTAEB1XR IDT, Integrated Device Technology Inc, IDTSTAC9758XXTAEB1XR Datasheet - Page 68

• Manufacturer Part Number: IDTSTAC9758XXTAEB1XR
• Description: IC CODEC AC'97 6CH 2.3 48-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Audio Codec '97r

Specifications of IDTSTAC9758XXTAEB1XR

• Data Interface: Serial
• Resolution (bits): 20 b
• Number Of Adcs / Dacs: 2 / 3
• Sigma Delta: Yes
• Voltage - Supply, Analog: 3.14 V ~ 3.47 V; 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 3.135V
• Single Supply Voltage (max): 3.465/5.25V
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: STAC9758XXTAEB1XR

IDT™
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
STAC9758/9759
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
8.2.18.
Bit(s) Reset Value R/W
14-13
15
12
11
D15
D7
I4
Audio Interrupt and Paging (24h)
Default: 0000h
0
0
0
0
D14
D6
I3
RW
RW
RW
RO
RESERVED
Name
I3-I2
I4
I1
I0
D13
D5
I2
0 = Interrupt is clear
1 = interrupt is set
Interrupt event is cleared by writing a 1 to this bit.
The interrupt bit will change regardless of condition of interrupt enable (I0)
status. An interrupt in the GPI in slot 12 in the ACLink will follow this bit
change when interrupt enable (I0) is unmasked.
Interrupt Cause
00 = Reserved
01 = Sense Cycle Complete, sense info available.
10 = Change in GPIO input status
11 = Sense Cycle Complete and Change in GPIO input status.
These bits will reflect the general cause of the first interrupt event
generated. It should be read after interrupt status has been confirmed as
interrupting. The information should be used to scan possible interrupting
events in proper pages.
Sense Cycle
0 = Sense Cycle not in Progress
1 = Sense Cycle Start.
Writing a 1 to this bit causes a sense cycle start if supported. If sense cycle
is not supported this bit is read only.
Interrupt Enable
0 = Interrupt generation is masked.
1 = Interrupt generation is un-masked.
The driver should not un-mask the interrupt unless ensured by the AC‘97
Controller that no conflict is possible with modem slot 12 - GPI
functionality. Some AC’97 2.2 compliant controllers may not support audio
CODEC interrupt infrastructure. In either case, software should poll the
interrupt status after initiating a sense cycle and wait for Sense Cycle Max
Delay to determine if an interrupting event has occurred.
D12
68
D4
I1
PG3
D11
D3
I0
Description
STAC9758/9759
PG2
D10
D2
RESERVED
PG1
D9
D1
PC AUDIO
PG0
V 1.2 1206
D8
D0