IDTSTAC9758XXTAEB1XR IDT, Integrated Device Technology Inc, IDTSTAC9758XXTAEB1XR Datasheet - Page 36

• Manufacturer Part Number: IDTSTAC9758XXTAEB1XR
• Description: IC CODEC AC'97 6CH 2.3 48-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Audio Codec '97r

Specifications of IDTSTAC9758XXTAEB1XR

• Data Interface: Serial
• Resolution (bits): 20 b
• Number Of Adcs / Dacs: 2 / 3
• Sigma Delta: Yes
• Voltage - Supply, Analog: 3.14 V ~ 3.47 V; 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 3.135V
• Single Supply Voltage (max): 3.465/5.25V
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: STAC9758XXTAEB1XR

IDT™
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
STAC9758/9759
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
5.3.1.
5.3.2.
resolution of the implemented DAC (16, 18 or 20-bit), no DC biasing will be introduced by the least
significant bits.
When mono audio sample streams are output from the AC‘97 Controller, it is necessary that BOTH
left and right sample stream time slots be filled with the same data.
Slot 0: TAG / CODEC ID
Within slot 0, the first bit is a global bit (SDATA_OUT slot 0, bit 15) which flags the validity for the
entire audio frame. If the “Valid Frame” bit is a 1, this indicates that the current audio frame contains
at least one time slot of valid data. The next 12 bit positions sampled by AC‘97 indicate which of the
corresponding 12 time slots contain valid data. In this way data streams of differing sample rates can
be transmitted across AC-Link at its fixed 48 KHz audio frame rate.
The two LSBs of Slot 0 transmit the CODEC ID used to distinguish Primary and Secondary CODEC
register access.
Slot 1: Command Address Port
The command port is used to control features, and monitor status (see AC-Link input frame Slots 1
and 2) for AC‘97 CODEC functions including, but not limited to, mixer settings, and power manage-
ment (refer to the control register section of this specification).
The control interface architecture supports up to 64 16-bit read/write registers, addressable on even
byte boundaries. Only the even registers (00h, 02h, etc.) are currently defined, odd register (01h,
03h, etc.) accesses are reserved for future expansion.
Note: The DAC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.
1-0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Frame Valid
Slot 1 Primary CODEC Valid Command Address bit (Primary CODEC only)
Slot 2 Primary CODEC Valid Command Data bit (Primary CODEC only)
Slot 3-12 - Slot-Valid-Data bits
Reserved (Set to 0)
2-bit CODEC ID field (00 reserved for Primary; 01, 10, 11 indicate Secondary)
Slot 3: PCM Left channel
Slot 6: Alternative PCM1 Left
Slot 7: Alternative PCM2 Left
Slot 8: Alternative PCM2 Right
Slot 9: Alternative PCM1 Right
Slot 10: SPDIF Left
Slot 12: Audio GPIO
Slot 4: PCM Right channel
Slot 5: Modem Line 1 (not used on STAC9758/9759)
Slot 11: SPDIF Right
Table 7. Output Slot 0 Bit Definitions
36
Description
STAC9758/9759
PC AUDIO
V 1.2 1206