MC68MH360ZP25VL Freescale Semiconductor, MC68MH360ZP25VL Datasheet - Page 96

• Manufacturer Part Number: MC68MH360ZP25VL
• Description: IC MPU QUICC ETHER 25MHZ 357PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Clear the ENR and ENT bits at the end of the initialization. The MODE setting for QMC
mode is 0b1010.
A typical setting would be:
Step 11. Initialize basic global multichannel parameters as follows. See Chapter 2, “QMC
Memory Organization,” for more information.
Step 12. Copy INTBASE to INTPTR (multichannel interrupt pointer). See Chapter 4,
“QMC Exceptions,” for more information.
• MCBASE: (multichannel base pointer) is a pointer to a 64-Kbyte buffer descriptor
• INTBASE: (interrupt table base pointer) - points to the interrupt table in external
• MRBLR: (maximum receive buffer length) - should be large (> 30) for better
• GRFTHR: (global receive frame threshold) - normally set to 1. For example:
• GRFCNT: (global receive frame count) - should be initialized to the same value as
GSMR_L = 0x0000_000A;
table in external memory. For example:
SCC1.MCBASE = 0x1_0000;
memory. For example:
SCC1.INTBASE = 0xF000;
performance and should be a multiple of 4 bytes. This is valid for HDLC only. For
example:
SCC1.MRBLR = 60;
SCC1.GRFTHR = 1;
GRFTHR. For example:
SCC1.GRFCNT = 1;
C_MASK32:CRC constant, 32-bit =0xDEBB20E3
SCC1.C_MASK32 = 0xDEBB20E3;
C_MASK16:CRC constant,16-bit=0xFOB8
SCC1.C_MASK16 = 0xF0B8;
SCC1.INTPTR = SCC1.INTBASE;
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QMC Supplement
/* enable QMC */
/* BD base located 0x1_0000 */
/* interrupt table base 0xF000 */
/* set receive buffer length to 60 */
/* 1 receive frame to interrupt */
/* 1 receive frame to interrupt */
/* init 32-bit CRC const */
/* init 16-bit CRC const */
/* init intptr */