MC68MH360ZP25VL Freescale Semiconductor, MC68MH360ZP25VL Datasheet - Page 53

• Manufacturer Part Number: MC68MH360ZP25VL
• Description: IC MPU QUICC ETHER 25MHZ 357PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

2.4.2.2 TSTATE—Tx Internal State (Transparent Mode)
TSTATE defines the internal transmitter state. The high byte of TSTATE defines the
function code/address type and the Motorola/Intel bit (bit 3) that should always be set to 1.
Figure 2-12 shows the TSTATE register for transparent mode.
For the MH360, TSTATE should be host-initialized to 0x3800_0000 before enabling the
channel—function code 8. Table 2-12 describes the TSTATE fields for the MH360 with
boldfaced parameters to be initialized by the user.
For the 860MH, TSTATE should be host-initialized to 0x3000_0000 before enabling the
channel—AT = 0. Note that for the 860MH bit 4 should always be zero as only bits 5–7
map to AT[1–3]
parameters to be initialized by the user.
Field
0–1
2
3
4–7
0–1
2
3
4
5–7
Field
Note: For the 68360, the bit numbering is reversed. See Appendix A for more information.
Table 2-12. TSTATE Field Descriptions for MH360 (Transparent Mode)
Table 2-13. TSTATE Field Descriptions for 860MH (Transparent Mode)
—
—
MOT
FC[3–0]
—
—
MOT
—
AT[1–3]
Name
Name
Figure 2-12. TSTATE—Tx Internal State (Transparent Mode)
0
1
Motorola/Intel bit
0 = The bus format is Intel format (little-endian).
1 = The system bus is considered to be organized in Motorola format (big-endian).
Function code—This field contains the function code for the transmitter DMA channel for data
buffers in external memory (transmit buffers). Function codes are needed by the memory
controller to decode a correct memory cycle and activate the correct handshaking.
.
0
1
Motorola/Intel bit
0 = The bus format is Intel format (little-endian).
1 = The system bus is considered to be organized in Motorola format (big-endian).
0
Address type—This field contains the address type for the transmitter DMA channel for data
buffers in external memory (transmit buffers). Address types are needed by the memory
controller to decode a correct memory cycle and activate the correct handshaking.
Table 2-13 describes the TSTATE fields for the 860MH with boldfaced
Freescale Semiconductor, Inc.
For More Information On This Product,
0
0
Chapter 2. QMC Memory Organization
1
0
Go to: www.freescale.com
2
1
MOT
3
4
Description
Description
FC[3–0]/ AT[1–3]
5
6
7