MC68MH360ZP25VL Freescale Semiconductor, MC68MH360ZP25VL Datasheet - Page 148

IC MPU QUICC ETHER 25MHZ 357PBGA

MC68MH360ZP25VL

Manufacturer Part Number
MC68MH360ZP25VL
Description
IC MPU QUICC ETHER 25MHZ 357PBGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68MH360ZP25VL

Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-

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Freescale Semiconductor, Inc.
C.3.2 MC145572 U Interface
The FREQREF signal of the MC145572 provides a clock synchronized to the network
timing for the U interface. This frequency reference is a fixed 2.048-MHz clock enabled by
setting OR8[4] in the MC145572 register set.
The U interface’s FREQREF differs from the TCLK of the S/T interface. When enabled,
the FREQREF signal generates the 2.048-MHz clock regardless of the activation status of
the U interface (but that clock is synchronized to the network only when the U interface is
activated). Also, FREQREF does not require the DCL and FSC signals to enable clock
generation.
Like the S/T interface, on the other hand, the FREQREF signal can be used as the DCL for
the IDL bus. When divided by 256, FREQREF can also be used to generate the 8-KHz
frame sync FSC. The same logic design used for the S/T interface must be added to insure
a correct FSC duty cycle; see Figure C-4.
Also like the S/T interface, elastic buffers are included to allow the U interface to operate
with any phase relationship between the IDL frame sync and the network.
Figure C-10 shows a block diagram of the connection between four U interfaces and the
QUICC32. The diagram would be the same for up to 10 U interfaces.
QMC Supplement
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