MC68MH360ZP25VL Freescale Semiconductor, MC68MH360ZP25VL Datasheet - Page 36

• Manufacturer Part Number: MC68MH360ZP25VL
• Description: IC MPU QUICC ETHER 25MHZ 357PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Offset
Base
SCC
0A
0C
0E
06
08
10
14
to
MRBLR
Tx_S_PTR
RxPTR
GRFTHR
GRFCNT
INTBASE
INTPTR
Name
Table 2-1. Global Multichannel Parameters (Continued)
Freescale Semiconductor, Inc.
16
16
16
16
16
32
32
For More Information On This Product,
Width
(Bits)
starting address of the interrupt circular queue in external memory. Each entry
contains information about an interrupt request that has been generated by the
QMC to the host. Each SCC operating in QMC mode has its own interrupt table
in external memory.
See Chapter 4, “QMC Exceptions.”
Multichannel interrupt pointer (host-initialized)—This global parameter holds the
address of the next QMC interrupt entry in the circular interrupt table. The RISC
processor writes the next interrupt information to this entry when an exception
occurs. The host must copy the value of INTBASE to INTPTR before enabling
interrupts.
Maximum receive buffer length—This host-initialized entry defines the
maximum number of bytes written to a receive buffer before moving to the next
buffer for this channel. This parameter is only valid in HDLC mode.
The buffer area allocated in memory for each buffer is MRBLR + 4. The QMC
adds another long word if non-octet-aligned frames are received in HDLC
operation. The non-octet information is written only to the last buffer of a frame,
but it can happen in any buffer. See Section 5.1, “Receive Buffer Descriptor,” for
more information.
As the QMC works on long-word alignment, MRBLR value should be a multiple
of 4 bytes.
Tx time slot assignment table pointer (SCC base + 60 in normal mode; SCC
base + 20 for common Rx & Tx time slot assignment tables)—This global QMC
parameter defines the start value of the TSATTx table. The TSATTx table in the
global multichannel parameter listing starts by default at SCC base + 60.
Tx_S_PTR lets the user move the starting address of this table. If the same
routing and masking are used for the transmitter and receiver, the tables can be
overlaid, so Tx_S_PTR can point to SCC base + 20. This parameter is an offset
from DPRBASE. This table must be present only once per SCC global area.
Other SCCs can access this location.
Rx pointer (initialize to SCC base + 20)—This global QMC parameter is a RISC
variable that points to the current receiver time slot. The host must initialize this
pointer to the starting location of TSATRx. The RISC processor increments this
pointer whenever it completes the processing of a received time slot.
Global receive frame threshold—Used to reduce interrupt overhead when many
short HDLC frames arrive, each causing an RXF interrupt. GRFTHR can be set
to limit the frequency of interrupts. Note that the RXF event is written to the
interrupt table on each received frame, but GINT is set only when the number of
RXF events (by all channels) reaches the GRFTHR value. GRFTHR can be
changed on the fly. For information about exception handling, see Chapter 4,
“QMC Exceptions.”
Global receive frame count (initialized GRFCNT = GRFTHR)—A down-counter
used to implement the GRFTHR feature. GRFCNT decrements for each frame
received. No other receiver interrupts affect this counter. The counter value is
set to the threshold during initialization. GRFCNT is automatically reset to the
GRFTHR value by the CPM after a global interrupt.
Multichannel interrupt base address (host-initialized)—This pointer contains the
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QMC Supplement
Description