MC68MH360ZP25VL Freescale Semiconductor, MC68MH360ZP25VL Datasheet - Page 76

• Manufacturer Part Number: MC68MH360ZP25VL
• Description: IC MPU QUICC ETHER 25MHZ 357PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Figure 5-4 shows a TXB interrupt generated after (PAD + 1) flag characters following the
closing flag. Four flags (NOF = 3) precede the next data. To set up this sequence correctly,
the PAD value must not exceed NOF.
6
7
8
9–11
12–15
16–31
32–63
Field
Table 5-2. Transmit Buffer Descriptor (TxBD) Field Descriptions (Continued)
Name
CM
—
UB
—
PAD
DL
TxBP
Continuous mode
0 Normal operation.
1 The R bit is not cleared by the CPM after this buffer descriptor is closed, allowing the
—
User bit—The CPM never touches, sets, or clears this user-defined bit. The user determines how
this bit is used. For example, it can be used to signal between higher-level protocols whether a
buffer has been processed by the CPU.
—
Padding bits—These four bits indicate the number of PAD characters (0x7E or 0xFF depending
on IDLM mode in the CHAMR register) that the transmitter sends after the closing flag. The
transmitter issues a TXB interrupt only after sending the programmed value of pads to the Tx
FIFO. The user can use the PAD value to guarantee that a TXB interrupt occurs after the closing
flag has been sent on the TXD line. PAD = 0 means the TXB interrupt is issued immediately after
sending the closing flag to the Tx FIFO.
The number of PAD characters depends on the FIFO size and the number of time slots in use. An
example explains the calculation: In SCC1 the FIFO is 32 bytes. If 16 time slots are used in the
link, the resulting number of PAD characters is 32/16 = 2, to append to this buffer to ensure that
the TXB interrupt is not given before the closing flag has been transmitted through the TXD line.
The number of PAD characters must not exceed the NOF characters, ensuring that the closing of
one buffer (the interrupt generation) occurs before the start of the next frame (clearing of R-bit).
After the sequence of a closing flag followed by (PAD + 1) flag characters, a TXB interrupt will be
generated; see Figure 5-4.
Data length—The data length is the number of bytes the CPM should transmit from this buffer
descriptor’s data buffer. It is never modified by the CPM. This field should be greater than zero.
Tx buffer pointer—The transmit buffer pointer, which contains the address of the associated data
buffer, may be even or odd. The buffer may reside in either internal or external memory. This
value is never modified by the CPM.
PAD=1, NOF=3
associated data buffer to be retransmitted automatically when the CPM next accesses this
buffer descriptor.
Freescale Semiconductor, Inc.
DATA
For More Information On This Product,
Figure 5-4. Relation between PAD and NOF
CRC
TXB INTERRUPT
Go to: www.freescale.com
FLG
QMC Supplement
FLG
Description
FLG
CLEARING R-BIT
FLG
DATA