MC68MH360ZP25VL Freescale Semiconductor, MC68MH360ZP25VL Datasheet - Page 37

• Manufacturer Part Number: MC68MH360ZP25VL
• Description: IC MPU QUICC ETHER 25MHZ 357PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Offset
Base
SCC
1A
1C
A0
A4
A8
18
20
60
to
Rx_S_PTR
TxPTR
C_MASK32
TSATRx
TSATTx
C_MASK16
TEMP_RBA
TEMP_CRC
Name
Table 2-1. Global Multichannel Parameters (Continued)
Freescale Semiconductor, Inc.
16
16
32
32
Entries
32
Entries
x 16
16
32
32
For More Information On This Product,
Width
(Bits)
x 16
Chapter 2. QMC Memory Organization
Time slot assignment table Tx—Maps a specific logical channel to each
physical time slot. Time slot assignment table Tx is a host-initialized, 16-bit table
with 32 entries that define the mapping of channels to time slots for the QMC
transmitter. The QMC protocol looks at chunks of 8 bits regardless if they go to
one physical time slot of the TDM or whatever other combination of bits are
transferred from the SCC to the TDM through the TSA. These 8 bits are referred
to as a time slot in the assignment table. It is recommended but not required to
route all bits from the TDM to the SCC and to do all enabling and masking in the
time slot assignment table. See Figure 2-3.
constant is written by the host during QMC initialization. It is used for 16-bit
CRC-CCITT calculation if HDLC mode of operation is chosen for a selected
channel. (This is a programmable option. For each HDLC channel, one of two
CRCs can be chosen, as programmed in CHAMR.) For more information, see
Section 2.4.1, “Channel-Specific HDLC Parameters,” and Table 2-5. This entry
must have a correct value if at least one HDLC channel is used; otherwise, it
can be cleared (0).
Rx time-slot assignment table pointer (default = SCC base + 20 in normal
mode)—This global QMC parameter defines the start value of the TSATRx
table, which must be present only once per SCC global area. Other SCCs may
access this location.
TxPTR (initialize to SCC Base + 60)—This global parameter is a RISC variable
that points to the current transmitter time slot. The host must initialize it to the
starting location of TSATTx. The RISC processor increments this pointer
whenever it completes the processing of a transmitter time slot.
CRC constant (0xDEBB20E3)—Required to calculate 32-bit CRC-CCITT.
C_MASK32 is written by the host during QMC initialization. It is used for 32-bit
CRC-CCITT calculation if HDLC mode of operation is chosen for a selected
channel. (This is a programmable option. For each HDLC channel, one of two
CRCs can be chosen, as programmed in CHAMR.) For more information, see
Section 2.4.1, “Channel-Specific HDLC Parameters,” and Table 2-5. This entry
must have a correct value if at least one HDLC channel is used; otherwise, it
can be cleared (0).
Time slot assignment table Rx—Host-initialized, 16-bit-wide table with 32
entries that define mapping of logical channels to time slots for the QMC
receiver. The QMC protocol looks at chunks of 8 bits regardless of whether they
come from one physical time slot of the TDM or whatever other combination of
bits the TSA transfers to the SCC. These 8 bits are referred to as a time slot in
the assignment table. It is recommended but not required to route all bits from
the TDM to the SCC and to do all enabling and masking in the time-slot
assignment table. See Figure 2-3.
CRC constant (0xF0B8)—Required to calculate 16-bit CRC-CCITT. This
Temporary receive buffer address
Temporary cyclic redundancy check
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Description