MC68MH360ZP25VL Freescale Semiconductor, MC68MH360ZP25VL Datasheet - Page 150

• Manufacturer Part Number: MC68MH360ZP25VL
• Description: IC MPU QUICC ETHER 25MHZ 357PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

C.3.2.1 Activation Procedure
During the initialization, the FREQREF signal of each U interface is enabled.
A multiplexer commanded by the QUICC32 is used to select the U interface clock master.
When the first MC145572 is activated, its FREQREF signal synchronizes to the network.
The MC145572 then sends an interrupt to the QUICC32 (IRQ1— register NR3[1]—
meaning uao = 1 has been received) indicating that the activation process has begun. Before
responding to LT with act = 1 (which will enable the data transfer), the QUICC32 can
select, through the multiplexer, this particular FREQREF signal to be the clock master.
Since the QUICC32 has the initiative to enable the data transfer, there is no timing
constraint to react to the interrupt.
C.3.2.2 Deactivation Procedure
According to the ANSI specification T1.601-1988, prior to deactivating, the LT should
notify the NT of the pending deactivation by clearing the M4 channel dea bit towards the
NT for at least three superframes. Then, the NT can be deactivated by sending a
deactivation request.
The MC145572 not only has the ability to generate an interrupt after the reception of the
third dea bit = 0, but also after the reception of the second dea bit = 0.
When the clock-master U interface is deactivated, the QUICC32 receives an interrupt
indicating that the second dea bit = 0 has been received. The QUICC32 has then the ability
to select another activated U interface (if there is one), to be the clock master. The
QUICC32 has 12 ms (1 superframe) until receiving the next dea bit = 0, indicating the
pending deactivation, and therefore 12 ms to react to the interrupt.
If none of the U interfaces are activated, no change in the multiplex selection is required.
C.3.3 System Configuration
The following sections provide a checklist of the main features that need to be configured
for each device.
C.3.3.1 S/T-Interface Configuration
Do the following for an S/T-interface configuration:
• IDL2 with time slot assigner (TSA enabled in reg. OR6[5–7]; TSA selection in
• Slave mode (DCL & FSC are input) - (pin M/S to GND)
• TCLK enabled at 2.048 MHz (OR7[5] = 1; BR13[5] = 0;
• D channel contention procedure disabled (BR7[6] = 1)
OR0 to OR5)
BR7[2] = 1)
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