MC68MH360ZP25VL Freescale Semiconductor, MC68MH360ZP25VL Datasheet - Page 26

• Manufacturer Part Number: MC68MH360ZP25VL
• Description: IC MPU QUICC ETHER 25MHZ 357PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

1.7 SCC Changes on the Fly
Changes can be made on the fly in the QMC routing tables, but changes made in the SI
RAM require the link to be disconnected. If the connection is maintained during changes,
synchronization and routing errors are likely to happen in the current frame. A workaround
uses a shadow RAM routing table. The shadow table can hold alternative routing
information to be switched in at the appropriate time slot boundary. The drawback to this
method is that the number of entries in the SI RAM is reduced by half. But since the routing
tables in the QMC protocol are being changed anyway, the recommended solution is to
have all relevant time slots routed to the SCC.
The SI RAM also gives the user the capability to multiplex other channels to and from a
TDM if not all time slots are used by the QMC. A third option is to have several external
devices multiplexed. Use the open collector mode if several QUICCs or PowerQUICCs are
connected together for subchanneling applications.
1.8 SI RAM Errors
The following three types of errors are identified:
Errors in frame-based protocols are easy to detect by the protocol controller. An error in an
HDLC channel is detected at the end of a frame when a buffer is closed and all status bits
are reported in the buffer descriptor (BD). The error type for bit errors is normally CRC
errors. For errors occurring in the SI (noise on clock or synchronization pulses), the error
may also be of type frame-length-violation or non-octet-aligned. See Chapter 5, “Buffer
Descriptors,” for more information. This section covers the type of errors reported through
the buffer descriptors. For transparent channels, the error detection mechanism is left to the
user in higher-level software. Most transparent channels, such as voice carriers, are tolerant
of errors. Frame-based channels, on the other hand, require error detection since they often
rely on critical control messages.
The number of clocks that occur between sync pulses is given in the SI RAM programming.
The clock-counting state machine expects a new sync pulse after the end of each frame. The
following paragraphs discuss the different error cases and describe the counter state and the
frame delay before synchronization is resumed.
A clock pulse error occurs if other than exactly one clock pulse is detected by the SI RAM
in a given frame. In this error case, since the SI RAM bases its routing on counting clock
pulses, the now corrupted signal routing affects all channels. The SI RAM expects another
sync pulse when it reaches the last entry of the frame.
• Data bit error
• Clock pulse error
• Synchronization pulse error
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QMC Supplement