MC68MH360ZP25VL Freescale Semiconductor, MC68MH360ZP25VL Datasheet - Page 40

• Manufacturer Part Number: MC68MH360ZP25VL
• Description: IC MPU QUICC ETHER 25MHZ 357PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

If the transmitter and receiver have the same mapping then it is possible to use a common
time slot assignment table. This is initialized by setting both Tx_S_PTR and Rx_S_PTR to
SCC Base + 20. For 64-channel support it is suggested to use common Rx and Tx
parameters. The time slot assignment table will then also be common and have 64 entries
starting at SCC Base + 20; see Figure 2-4.
2.3 Multiple SCC Assignment Tables
Assume a scenario as depicted in Figure 2-5. A 2.048-Mbps TDM link is fed directly into
the TSA. Within the SI RAM, the even channels (byte-wide) are muxed to SCC3 and the
odd channels are muxed to SCC2. This arrangement is used to spread the load over two
SCCs. This effectively doubles the FIFO depth on the QMC protocol. Time slots are
switched to alternate SCCs to avoid data bursts that may stress the FIFOs. Each SCC sees
a continuous bitstream without any gaps as described earlier.
Note: For the 68360, the bit numbering is reversed. See Appendix A for more information.
Figure 2-4. Time Slot Assignment Table for 64-Channel Common Rx and Tx
Time Slot 62
Time Slot 63
Time Slot 1
Time Slot 0
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QMC Supplement
Mapping
Channel Pointer
Channel Pointer
Channel Pointer
Channel Pointer
Channel Pointer
Channel Pointer
Channel Pointer
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64 x 16