MC68MH360ZP25VL Freescale Semiconductor, MC68MH360ZP25VL Datasheet - Page 132

• Manufacturer Part Number: MC68MH360ZP25VL
• Description: IC MPU QUICC ETHER 25MHZ 357PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

B.2 860MH-Related Questions
Q: Is Ethernet only available on SCC1 for both 860EN and 860MH?
A: Ethernet is available on any channel. We recommend it on SCC1 due to its larger
Q: How is 64-channel QMC implemented on the 50-MHz 860MH? What is the serial
A: Use two SCCs running 32-channel QMC protocol. Each channel is assumed to be
Q: Does running transparent-mode processing on the QMC channels decrease the load
A: CPM loading in transparent mode is not significantly different from the loading in
Q: How many channelized T1/E1 ports does the 860MH support? (where E1 is thirty-
A: With respect to running multiple channels of HDLC, the major limitation of the
Q: How is the 860MH configured to support more than 32 channels.
A: The QMC protocol for the 860MH can be used to support more than 32 HDLC
Therefore, a 50-MHz MPC860MH will be needed to run 64 channels of HDLC on
one device.
FIFO.
speed of the TDM channels?
64-Kbps, like a normal time slot on a T1/E1 line, giving an aggregate rate of 4 Mbps
(that is, twice the E1 rate).
on the CPM?
HDLC mode; therefore, performance will be the same.
two 64-Kbps channels and T1 is 24 channels)
current 860MH is clock frequency. A 25-MHz part can run only 32 HDLC channels,
while a 50-MHz part can run 64 channels. At this point, however, the size of the
dual-ported RAM limits the number of HDLC channels to 64.
The MPC860 also has just two time slot assigners. Therefore, it can directly
terminate at most two T1s or E1s.
channels in three ways:
• In one method, use shared transmit/receive channel routing on one SCC to run
• In another method, run the QMC protocol on two separate SCCs, each with its
the QMC protocol linking the maximum of 64 time slots of a single multiplexed
line to 64 separate logical channels.
own set of parameters. With this method, two separate E1s can be routed to the
two separate SCCs. It is not possible, however, to share channels from both E1s
at random between the SCCs. (One E1 will map to the 32 logical channels of one
SCC.)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
QMC Supplement