MC68340AG25E Freescale Semiconductor, MC68340AG25E Datasheet - Page 363

• Manufacturer Part Number: MC68340AG25E
• Description: IC MPU 32BIT 25MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG25E

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 25MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 25 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

STP—Stop bit
FRZ1, FRZ0—Freeze
Bits 12–8, 6–4—Reserved
SUPV—Supervisor/User
IARB3–IARB0—Interrupt Arbitration Bits
MOTOROLA
These bits determine the action taken when the FREEZE signal is asserted on the IMB,
when the CPU32 has entered background debug mode. Table 8-2 lists the action taken
for each bit combination.
The value of this bit has no effect on registers permanently defined as supervisor-only
access.
Each module that generates interrupts has an IARB field. These bits are used to
arbitrate for the bus in the case that two or more modules simultaneously generate an
interrupt at the same priority level. No two modules can share the same IARB value.
(Timer 1 and timer 2 should be programmed with different values if both are used.) The
reset value of the IARB field is $0, which prevents this module from arbitrating during
the interrupt acknowledge cycle. The system software should initialize the IARB field to
a value from $F (highest priority) to $1 (lowest priority).
1 = Setting the STP bit stops all clocks within the timer module except for the clock
0 = The timer operates in normal mode.
1 = The timer registers defined as supervisor/user reside in supervisor data space
0 = The timer registers defined as supervisor/user reside in user data space and are
from the IMB. The clock from the IMB remains active to allow the CPU32 access
to the MCR. The clock stops on the low phase of the clock and remains stopped
until the STP bit is cleared by the CPU32 or a hardware reset. Accesses to timer
module registers while in stop mode produce a bus error. The timer module
should be disabled in a known state prior to setting the STP bit; otherwise,
unpredictable results may occur. The STP bit should be set prior to executing the
LPSTOP instruction to reduce overall power consumption.
and are only accessible from supervisor programs.
accessible from either supervisor or user programs.
Freescale Semiconductor, Inc.
FRZ1
For More Information On This Product,
0
0
1
1
Table 8-2. FRZx Control Bits
FRZ0
MC68340 USER’S MANUAL
Go to: www.freescale.com
0
1
0
1
Ignore FREEZE
Reserved (FREEZE ignored)
Execution Freeze
Execution Freeze
ACTION
8- 19