MC68340AG25E Freescale Semiconductor, MC68340AG25E Datasheet - Page 202
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MC68340AG25E
Manufacturer Part Number
MC68340AG25E
Description
IC MPU 32BIT 25MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68340FE25E.pdf
(441 pages)
Specifications of MC68340AG25E
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
144-LQFP
Controller Family/series
68K
Core Size
32 Bit
No. Of I/o's
16
Cpu Speed
25MHz
No. Of Timers
2
Embedded Interface Type
UART
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Processor Series
M683xx
Core
CPU32
Maximum Clock Frequency
25 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Details
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
MC68340AG25E
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MC68340AG25E
Manufacturer:
Freescale Semiconductor
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memory access. Off-chip address comparators will not detect breakpoints on internal
accesses unless show cycles are enabled. Breakpoints on prefetched instructions, which
are flushed from the pipeline before execution, are not acknowledged, but operand
breakpoints are always acknowledged. Acknowledged breakpoints can initiate either
exception processing or BDM. See 5.5.2.6 Hardware Breakpoints for more information.
5.6.2 Background Debug Mode
BDM is an alternate CPU32 operating mode. During BDM, normal instruction execution is
suspended, and special microcode performs debugging functions under external control.
Figure 5-20 is a BDM block diagram.
BDM can be initiated in several ways—by externally generated breakpoints, by internal
peripheral breakpoints, by the background instruction (BGND), or by catastrophic
exception conditions. While in BDM, the CPU32 ceases to fetch instructions via the
parallel bus and communicates with the development system via a dedicated, high-speed,
SPI-type serial command interface.
5.6.2.1 ENABLING BDM. Accidentally entering BDM in a nondevelopment environment
could lock up the CPU32 since the serial command interface would probably not be
available. For this reason, BDM is enabled during reset via the BKPT signal.
MOTOROLA
MICROCODE
EXECUTION
UNIT
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 5-20. BDM Block Diagram
BERR
BKPT
IRC
SEQUENCER
MC68340 USER’S MANUAL
Go to: www.freescale.com
BERR
BKPT
IRB
INTERFACE
SERIAL
BERR
BKPT
IR
CONTROL
BUS
IPIPE/DSO
IFETCH/DSI
BKPT/DSCLK
DATA BUS
BERR
FREEZE
. . . . . . .
ADDRESS BUS
5- 65
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