MC68340AG25E Freescale Semiconductor, MC68340AG25E Datasheet - Page 171

• Manufacturer Part Number: MC68340AG25E
• Description: IC MPU 32BIT 25MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG25E

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 25MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 25 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

The following value has been calculated for independent variable X:
Since X is an 8-bit value, the upper four bits are used as a table offset and the lower four
bits are used as an interpolation fraction. The following results are obtained from the
subroutine:
Thus, Y is calculated as follows:
If the 8-bit value for X were used directly by the table instruction, interpolation would be
incorrectly performed between entries 0 and 1. Data must be shifted to the left four places
before use:
The new range for X is 0
digits of the word with zeros, the interpolation fraction can only have one of 16 values.
After the shift operation, Dx contains the following value:
Execution of the table instruction using the new value in Dx yields:
Thus, Y is calculated as follows:
5.3.4.4 TABLE EXAMPLE 4: MAINTAINING PRECISION. In this example, three TBL
operations are performed and the results are summed. The calculation is done once with
the result of each TBL rounded before addition and once with only the final result rounded.
Assume that the result of the three interpolations are as follows (a ".'' indicates the binary
radix point).
5-34
31
31
NOT USED
NOT USED
Interpolation Fraction
Table Entry Offset
Interpolation Fraction
Freescale Semiconductor, Inc.
Table Entry Offset
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TBL # 1
TBL# 2
TBL # 3
Y = 80
X
Y = 80
4096; however, since a left shift fills the least significant
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(208 (64 – 80)) / 256 = 67
(13 (64 – 80)) / 16 = 67
LSL.W #4, Dx
16
16
0010 0000 . 0111 0000
0011 1111 . 0111 0000
0000 0001 . 0111 0000
Dx [8:15] = $0B = 11
15
15
0
0
Dx [0:7] = $D0 = 208
Dx [4:7] = $B = 11
0
0
Dx [0:3] = $D = 13
0
0
0
0
0
1
0
0
0
1
0
1
1
1
0
1
1
0
1
1
MOTOROLA
1
0
1
0
0
0
0
1
0
0