MC68340AG25E Freescale Semiconductor, MC68340AG25E Datasheet - Page 285

• Manufacturer Part Number: MC68340AG25E
• Description: IC MPU 32BIT 25MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG25E

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 25MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 25 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

This register is decremented by 1, 2, or 4 for each successful operand transfer from
source to destination locations. When the BTC decrements to zero and no error has
occurred, the CSR DONE bit is set. In the external request mode, the DONE handshake
line is also asserted when the BTC is decremented to zero.
If the operand size is byte, then the register is always decremented by 1. If the operand
size is word and the starting count is even word, the register is decremented by 2. If the
operand size is word and the byte count is not a multiple of 2, the CSR CONF bit is set,
and a transfer does not occur. If the operand size is long word and the count is even long
word, then the register is decremented by 4. If the operand size is long word and the byte
count is not a multiple of 4, the CSR CONF bit is set, and a transfer does not occur. If the
STR bit is set with a zero count in the BTC, the CONF bit is set, and the STR bit is
cleared.
When read, this register always contains the count for the next access. If a bus error
terminates the transfer, this register contains the count for the next access that would
have been run had the error not occurred.
6.8 DATA PACKING
The internal DHR is a 32-bit register that can serve as a buffer register for the data being
transferred during dual-address DMA cycles. No address is specified since this register
can not be addressed by the programmer. The DHR allows the data to be packed and
unpacked by the DMA during the dual-address transfer. For example, if the source
operand size is byte and the destination operand size is word, then two-byte read cycles
occur, followed by a one-word write cycle (see Figure 6-16). The two bytes of data are
buffered in the DHR until the destination (write) word cycle occurs. The DHR allows for
packing and unpacking of operands for the following sizes: bytes to words, bytes to long
words, words to long words, words to bytes, long words to bytes, and long words to words.
MOTOROLA
SOURCE/DESTINATION
BYTE0
BYTE2
BYTE0
BYTE1
BYTE0
BYTE1
BYTE2
BYTE3
Figure 6-16. Packing and Unpacking of Operands
BYTE1
BYTE3
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BYTE0
BYTE0
DESTINATION/SOURCE
. . . . . . . . . . . . . . . . . . . . .
BYTE0
BYTE1
BYTE1
BYTE1
BYTE2
BYTE2
BYTE3
BYTE3
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