MC68340AG25E Freescale Semiconductor, MC68340AG25E Datasheet - Page 207

• Manufacturer Part Number: MC68340AG25E
• Description: IC MPU 32BIT 25MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG25E

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 25MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 25 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

The serial state machine begins a sequence of events based on the rising edge of the
synchronized DSCLK (see Figure 5-23). Synchronized serial data is transferred to the
input shift register, and the received bit counter is decremented. One-half clock period
later, the output shift register is updated, bringing the next output bit to the DSO signal.
DSO changes relative to the rising edge of DSCLK and does not necessarily remain
stable until the falling edge of DSCLK.
One clock period after the synchronized DSCLK has been seen internally, the updated
counter value is checked. If the counter has reached zero, the receive data latch is
updated from the input shift register. At this same time, the output shift register is reloaded
with the “not ready/come again” response. Once the receive data latch has been loaded,
the CPU is released to act on the new data. Response data overwrites the “not ready”
response when the CPU has completed the current operation.
Data written into the output shift register appears immediately on the DSO signal. In
general, this action changes the state of the signal from a high (“not ready” response
status bit) to a low (valid data status bit) logic level. However, this level change only
occurs if the command completes successfully. Error conditions overwrite the “not ready”
response with the appropriate response that also has the status bit set.
5-70
MICROSEQUENCER
SYNCHRONIZE
EXECUTION
STATUS
UNIT
Figure 5-22. Debug Serial I/O Block Diagram
Freescale Semiconductor, Inc.
For More Information On This Product,
RCV DATA LATCH
PARALLEL OUT
REGISTER BUS
PARALLEL IN
INSTRUCTION
SERIAL OUT
SERIAL IN
MC68340 USER’S MANUAL
CPU
Go to: www.freescale.com
16
16
CONTROL
LOGIC
DSCLK
DSO
DSI
STATUS
0
. .
DEVELOPMENT SYSTEM
COMMAND LATCH
PARALLEL OUT
RESULT LATCH
CONTROL
PARALLEL IN
SERIAL OUT
LOGIC
SERIAL IN
DATA
DATA
16
16
MOTOROLA
SERIAL
CLOCK