MC68340AG25E Freescale Semiconductor, MC68340AG25E Datasheet - Page 177
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MC68340AG25E
Manufacturer Part Number
MC68340AG25E
Description
IC MPU 32BIT 25MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68340FE25E.pdf
(441 pages)
Specifications of MC68340AG25E
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
144-LQFP
Controller Family/series
68K
Core Size
32 Bit
No. Of I/o's
16
Cpu Speed
25MHz
No. Of Timers
2
Embedded Interface Type
UART
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Processor Series
M683xx
Core
CPU32
Maximum Clock Frequency
25 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Details
Available stocks
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Quantity
Price
Company:
Part Number:
MC68340AG25E
Manufacturer:
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Quantity:
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MC68340AG25E
Manufacturer:
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All exception vectors, except the reset vector, are located in supervisor data space. The
reset vector is located in supervisor program space. Only the initial reset vector is fixed in
the processor memory map. When initialization is complete, there are no fixed
assignments. Since the VBR stores the vector table base address, the table can be
located anywhere in memory. It can also be dynamically relocated for each task executed
by an operating system.
Each vector is assigned an 8-bit number. Vector numbers for some exceptions are
obtained from an external device; others are supplied by the processor. The processor
multiplies the vector number by 4 to calculate vector offset, then adds the offset to the
contents of the VBR. The sum is the memory address of the vector.
5.5.1.1 TYPES OF EXCEPTIONS. An exception can be caused by internal or external
events.
An internal exception can be generated by an instruction or by an error. The TRAP,
TRAPcc, TRAPV, BKPT, CHK, CHK2, RTE, and DIV instructions can cause exceptions
during normal execution. Illegal instructions, instruction fetches from odd addresses, word
or long-word operand accesses from odd addresses, and privilege violations also cause
internal exceptions.
Sources of external exception include interrupts, breakpoints, bus errors, and reset
requests. Interrupts are peripheral device requests for processor action. Breakpoints are
used to support development equipment. Bus error and reset are used for access control
and processor restart.
5.5.1.2 EXCEPTION PROCESSING SEQUENCE. For all exceptions other than a reset
exception, exception processing occurs in the following sequence. Refer to 5.5.2.1 Reset
for details of reset processing.
As exception processing begins, the processor makes an internal copy of the SR. After
the copy is made, the processor state bits in the SR are changed—the S-bit is set,
establishing supervisor access level, and bits T1 and T0 are cleared, disabling tracing. For
reset and interrupt exceptions, the interrupt priority mask is also updated.
Next, the exception number is obtained. For interrupts, the number is fetched from CPU
space $F (the bus cycle is an interrupt acknowledge). For all other exceptions, internal
logic provides a vector number.
Next, current processor status is saved. An exception stack frame is created and placed
on the supervisor stack. All stack frames contain copies of the SR and the PC for use by
RTE. The type of exception and the context in which the exception occurs determine what
other information is stored in the stack frame.
5-40
Because there is no protection on the 64 processor-defined
vectors, external devices can access vectors reserved for
internal purposes. This practice is strongly discouraged.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68340 USER’S MANUAL
Go to: www.freescale.com
CAUTION
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